Norio Nakagawa

SH4 RISC multimedia microprocessor

Unique, floating-point length-4 vector instructions prove more effective than conventional SIMD architecture for 3D graphics processing.

The Gmicro/500 superscalar microprocessor with branch buffers

The Gmicro/500, which features a RISC-like dual-pipeline structure for high-speed execution of basic instructions and represents a significant advance for the TRON architecture, is presented. Upwardly-object-compatible with earlier members of the Gmicro series, this microprocessor uses resident dedicated branch buffers to greatly enhance branch instruction execution speed. Its microprograms simultaneously use dual execution blocks to execute high-level language instructions effectively. Fabricated with a 0.6- mu m CMOS technology on a 10.9-mm*16-mm die, the chip operates at 50/66 MHz and achieves a processing rate of 100/132 MIPS.<<ETX>>

Functional verification of the superscalar SH-4 microprocessor

Functional verification of modern complex processors is a formidable and time consuming task. In spite of substantial manual effort, it is extremely difficult to systematically cover the corner cases of the control logic design, within a short processor design cycle. The SH4 processor is a dual issue superscalar RISC architecture with extensive hardware support for 3D graphics. We present the development of a semi automated methodology for functional verification. In particular, we elaborate a scheme to automatically generate test programs to verify the superscalar issue logic, bypass/multi bypass logic and stall logic, starting from the microarchitectural specification. Finally, we present the Random Test Generation methodology and the specific Random Test Generators.

A PA-RISC microprocessor PA/50L for low-cost systems

The PA/50L is a low-cost, low-power microprocessor from Hitachi Ltd. that is fully compatible with the PA-RISC architecture 1.1, third edition. This microprocessor achieves 55 VAX MIPS (Dhrystone 1.1), 10.6 MFLOPS (LINPACK inner loop) and 1.3 W at 33 MHz. In order to achieve high performance with no external cache, a non-blocking cache and a data prefetch instruction are provided. This paper gives an overview of the microprocessor and describes its capabilities.<<ETX>>