O. Bethge

Atomic layer deposition of ZrO2/La2O3 high-k dielectrics on germanium reaching 0.5 nm equivalent oxide thickness

We investigate ultrathin ZrO2/La2O3 high-k dielectric stacks on germanium grown by atomic layer deposition. La2O3 is deposited from tris(N,N′-diisopropylformamidinate)-lanthanum and oxygen. Interfacial layer-free oxide stacks with a relative dielectric constant of 21 and equivalent oxide thickness values as low as 0.5 nm are obtained. Metal oxide semiconductor capacitors with platinum as the gate electrode exhibit well-behaved capacitance-voltage characteristics, gate leakage current densities in the range of 0.01–1 A/cm2, and interface trap densities in the range of ∼3×1012 eV−1 cm−2.

Modeling small-signal response of GaN-based metal-insulator-semiconductor high electron mobility transistor gate stack in spill-over regime: Effect of barrier resistance and interface states

We provide theoretical and simulation analysis of the small signal response of SiO2/AlGaN/GaN metal insulator semiconductor (MIS) capacitors from depletion to spill over region, where the AlGaN/SiO2 interface is accumulated with free electrons. A lumped element model of the gate stack, including the response of traps at the III-N/dielectric interface, is proposed and represented in terms of equivalent parallel capacitance, Cp, and conductance, Gp. Cp -voltage and Gp -voltage dependences are modelled taking into account bias dependent AlGaN barrier dynamic resistance Rbr and the effective channel resistance. In particular, in the spill-over region, the drop of Cp with the frequency increase can be explained even without taking into account the response of interface traps, solely by considering the intrinsic response of the gate stack (i.e., no trap effects) and the decrease of Rbr with the applied forward bias. Furthermore, we show the limitations of the conductance method for the evaluation of the density...

Atomic layer-deposited platinum in high-k/metal gate stacks

Nanoscale platinum films are deposited by atomic layer deposition using trimethyl-methylcyclopentadienyl-platinum and oxygen as precursors on the high-k dielectrics ZrO2 and Al2O3, respectively, and on SiO2, issuing deposition temperature and precursor ratios. The ALD-grown platinum films are polycrystalline and show a preferential (1 1 1) orientation. The films are homogeneous with a root mean square roughness of 0.6–0.7 nm and reveal a low resistivity of 13.2 µΩ cm. The effective work functions are 4.76 eV for ZrO2, 5.22 eV for Al2O3 and 5.52 eV for SiO2. It is remarkable that the deposition temperature of the platinum metal gate influences the final equivalent oxide thickness. Comparing both, PVD and ALD platinum films, a decreased leakage current density is observed for the ALD films depending on ALD process conditions, along with an increase in the equivalent oxide thickness.

Pt-assisted oxidation of (100)-Ge/high-k interfaces and improvement of their electrical quality

We report on the improvement of electrical quality of (100)-Ge/high-k-dielectric interfaces by introducing thin Pt top layers on the dielectric and subsequent oxidative treatments or using a Pt-deposition process with inherent oxidative components. Here, deposition of thin physical vapor deposition-Pt layers, combined with subsequent oxygen treatments, or oxygen assisted atomic layer deposition of Pt on these dielectrics, is applied. Strong reduction of interface trap densities down to mid-1011 eV−1 cm−2 is achieved. The approach is shown for Pt/ZrO2/La2O3/Ge, Pt/ZrO2/GeO2/Ge, and Pt/ZrO2/Ge gate stacks. By x-ray photoelectron spectroscopy evidence is given for oxygen enrichment at Ge/high-k-dielectric interfaces, to be responsible for the improved electrical properties.

Fixed interface charges between AlGaN barrier and gate stack composed of in situ grown SiN and Al2O3 in AlGaN/GaN high electron mobility transistors with normally off capability

Using a generalized extraction method, the fixed charge density Nint at the interface between in situ deposited SiN and 5 nm thick AlGaN barrier is evaluated by measurements of threshold voltage Vth of an AlGaN/GaN metal insulator semiconductor high electron mobility transistor as a function of SiN thickness. The thickness of the originally deposited 50 nm thick SiN layer is reduced by dry etching. The extracted Nint is in the order of the AlGaN polarization charge density. The total removal of the in situ SiN cap leads to a complete depletion of the channel region resulting in Vth = +1 V. Fabrication of a gate stack with Al2O3 as a second cap layer, deposited on top of the in situ SiN, is not introducing additional fixed charges at the SiN/Al2O3 interface.

Process temperature dependent high frequency capacitance-voltage response of ZrO2/GeO2/germanium capacitors

ZrO2/GeO2 dielectrics are grown on germanium substrates by Atomic Layer Deposition (ALD) at substrate temperatures of 150, 200, and 250 °C, respectively. The impact of the deposition temperature on the electrical and structural properties of MOS capacitors is investigated. A significant influence of the ALD temperature on the high frequency capacitance in inversion can be observed, resulting in a shift of the minority carrier response time from 1.15 to 0.2 μs. Time-of-flight secondary ion mass spectroscopy investigations indicate a distinctive depletion of interfacial GeO at higher ALD temperatures, which give rise to trap levels near the oxide/Ge interface.

Ge p-MOSFETs With Scaled ALD

Dielectric thin films of La₂O₃/ZrO₂ deposited by atomic layer deposition (ALD) are investigated to be employed in Ge Schottky barrier p-MOSFETs. La₂O₃ is used as a thin passivation layer and is capped by atomic-layer-deposited ZrO₂ as a gate dielectric. As the gate contact TiN capped by W is applied, midgap-level trap densities of ~ 3-4 × 10¹² eV^-1 cm^-2 and subtreshold slopes down to 115-120 mV/dec are achieved. The devices show negative threshold voltages of -0.5 to -0.6 V, as well as peak hole mobility values of ~ 50-75 cm²/V · s. Equivalent oxide thickness (EOT) is reduced to 0.96 nm upon postmetallization annealing without degrading the interface properties. The results show the scaling potential of the ALD La₂O₃ interlayer capped with ZrO₂ gate dielectrics for the integration into sub-1-nm EOT Ge p-MOSFET devices.

\hbox{La}_{2} \hbox{O}_{3}/\hbox{ZrO}_{2}

In this work, the influence of the tip geometry in scanning capacitance microscopy is investigated experimentally and theoretically on metal-oxide-semiconductor- (MOS) and Schottky-type junctions on gallium-arsenide (GaAs). Using a two-dimensional model we find that on Schottky-type junctions the electric field around the tip is screened by the surface states and that the essential parameters entering the capacitance versus voltage C(V) characteristics are the doping level and the contact area only. In contrast to that, the electric field from the tip penetrates into the semiconductor on a MOS-type junction, and the tip geometry effects are much larger. C(V) spectra are fitted to the experimental data and allowed a quantitative determination of doping levels, oxide thickness, and contact area without further calibration measurements.

Gate Dielectrics

Polymeric nanowires of polypyrrole have been implemented as artificial cilia on giant-magneto-resistive multilayer sensors for a biomimetic sensing approach. The arrays were tagged with a magnetic material, the stray field of which changes relative to the underlying sensor as a consequence of mechanical stimuli which are delivered by a piezoactuator. The principle resembles balance sensing in mammals. Measurements of the sensor output voltage suggest a proof of concept at frequencies of around 190 kHz and a tag thickness of ∼300 nm. Characterization was performed by scanning electron microscopy and magnetic force microscopy. Micromagnetic and finite-element simulations were conducted to assess basic sensing aspects.

Tip geometry effects in scanning capacitance microscopy on GaAs Schottky and metal-oxide-semiconductor-type junctions

The impact of thermal post deposition annealing in oxygen at different temperatures on the Ge/Y2O3 interface is investigated using metal oxide semiconductor capacitors, where the yttrium oxide was grown by atomic layer deposition from tris(methylcyclopentadienyl)yttrium and H2O precursors on n-type (100)-Ge substrates. By performing in-situ X-ray photoelectron spectroscopy, the growth of GeO during the first cycles of ALD was proven and interface trap densities just below 1 × 1011 eV−1 cm−2 were achieved by oxygen annealing at high temperatures (550 °C–600 °C). The good interface quality is most likely driven by the growth of interfacial GeO2 and thermally stabilizing yttrium germanate.