O. Richard

Ternary rare-earth metal oxide high-k layers on silicon oxide

Ternary oxides, GdScO3, DyScO3, and LaScO3, deposited by pulsed laser deposition using ceramics targets of stoichiometric composition, were studied as alternative high-k gate dielectrics on (100) Si. Their physical characterization was done using Rutherford backscattering, spectroscopic ellipsometry, x-ray diffraction, and transmission electron microscopy on blanket layers deposited on (100) Si, and electrical characterization on capacitors. It is found that DyScO3 and GdScO3 preserve their amorphous phases up to 1000°C. Other encouraging properties for high k applications were demonstrated, including k-value ∼22, almost no hysteresis or frequency dispersion in C–V curves, and leakage current reduction comparable to that of HfO2 of the same equivalent oxide thickness.

Deposition of HfO2 on germanium and the impact of surface pretreatments

The deposition behavior of HfO2 by metalorganic chemical vapor deposition on germanium has been investigated. HfO2 films can be deposited on Ge with equally good quality as compared to high-k growth on silicon. Surface preparation is very important: compared to an HF-last, NH3 pretreatments result in smoother films with strongly reduced diffusion of germanium in the HfO2 film, resulting in a much better electrical performance. We clearly show that much thinner interfacial layers can be obtained, approximately half the thickness of what is typically found for depositions on silicon, suggesting the possibility of more aggressive equivalent oxide thickness∕leakage scaling.

Plasma-enhanced chemical vapour deposition growth of Si nanowires with low melting point metal catalysts: an effective alternative to Au-mediated growth

Au nanoparticles are efficient catalysts for the vapour?solid?liquid (VLS) growth of semiconductor nanowires, but Au poses fundamental reliability concerns for applications in Si semiconductor technology. In this work we show that the choice of catalysts for Si nanowire growth can be broadened when the need for catalytic precursor dissociation is eliminated through the use of plasma enhancement. However, in this regime the incubation time for the activation of VLS growth must be minimized to avoid burying the catalyst particles underneath an amorphous Si layer. We show that the combined use of plasma enhancement and the use of a catalyst such as In, already in a liquid form at the growth temperature, is a powerful method for obtaining Si nanowire growth with high yield. Si nanowires grown by this method are monocrystalline and generally oriented in the direction.

Analysis of the size effect in electroplated fine copper wires and a realistic assessment to model copper resistivity

The size effect in electroplated copper wires has been widely studied recently. However, there is no consensus on the role of various scattering mechanisms. Therefore, an in-depth analysis to reveal the origin of the size effect is needed. In this article, we study the resistivity of fine copper wires whose feature sizes shrink in two dimensions. It is shown that the residual resistivity (at 5 K) increases with decreasing wire width or height and the temperature-dependent resistivity slightly deviates from that of bulk copper. This is mainly attributed to surface scattering rather than grain boundary scattering. In fact, the influence of grain boundary scattering in these well annealed copper wires is relatively small. In addition, for copper wires with a constant height, a linear dependence of the copper resistivity on 1/width (w) or 1/cross-sectional area (A), namely ρ=ρic+c*∕w (or ρ=ρic+c**∕A), is derived from the classic surface and grain boundary scattering models and validated experimentally. In this simple description, the contributions of different scattering mechanisms, such as surface reflectivity, p, and grain boundary reflection coefficient, R, defect and impurity density, combine together in parameters of ρic and c* (or c**). Especially, c* is a good indicator of scattering strength, from which one can quantitatively analyze the impact of nonsurface scattering contribution with a reference slope of c*=32.14.The size effect in electroplated copper wires has been widely studied recently. However, there is no consensus on the role of various scattering mechanisms. Therefore, an in-depth analysis to reveal the origin of the size effect is needed. In this article, we study the resistivity of fine copper wires whose feature sizes shrink in two dimensions. It is shown that the residual resistivity (at 5 K) increases with decreasing wire width or height and the temperature-dependent resistivity slightly deviates from that of bulk copper. This is mainly attributed to surface scattering rather than grain boundary scattering. In fact, the influence of grain boundary scattering in these well annealed copper wires is relatively small. In addition, for copper wires with a constant height, a linear dependence of the copper resistivity on 1/width (w) or 1/cross-sectional area (A), namely ρ=ρic+c*∕w (or ρ=ρic+c**∕A), is derived from the classic surface and grain boundary scattering models and validated experimentally. In thi...

Surface preparation and interfacial stability of high-k dielectrics deposited by atomic layer chemical vapor deposition

The effects of various interface preparations on atomic layer chemical vapor deposition (ALCVD) deposited Al2O3 and ZrO2 dielectrics properties were investigated by X-ray photoelectron spectroscopy (XPS), attenuated total reflection Fourier transform infrared spectroscopy (ATR-FTIR), medium energy ion scattering (MEIS) and transmission electron microscopy (TEM). H-terminated Si, SiO2 and SiOxNy surfaces were used as substrates upon which the dielectric was deposited. Thermal annealing of SiO2 in NH3 forms an oxynitride; subsequent deposition of a ZrO2/Al2O3 bi-layer stack resulted in a capacitor structure with an equivalent oxide thickness (EOT) of ˜ 0.8 nm and a leakage current of 3 × 10-4 A/cm2 at - 1 + Vfb. This is in contrast to capacitor structures grown on H-terminated Si where high leakage was found. The growth of additional interfacial SiO2 during processing, a critical problem in nano-electronic device applications, is temperature dependent with ZrO2 exhibiting a higher oxygen permeability than Al2O3. Use of a polysilicon cap was shown to be effective at blocking oxygen absorption and transport through the high-k dielectrics, with stability up to 1100 °C.

Silicate formation and thermal stability of ternary rare earth oxides as high-k dielectrics

Hf-based dielectrics are currently being introduced into complementary metal oxide semiconductor transistors as replacement for SiON to limit gate leakage current densities. Alternative materials such as rare earth based dielectrics are of interest to obtain proper threshold voltages as well as to engineer a material with a high thermal stability. The authors have studied rare earth based dielectrics such as Dy2O3, DyHfOx, DyScOx, La2O3, HfLaOx, and LaAlOx by means of ellipsometry, time of flight secondary ion mass spectroscopy x-ray diffraction, and x-ray photoelectron spectroscopy. The authors show that ellipsometry is an easy and powerful tool to study silicate formation. For ternary rare earth oxides, this behavior is heavily dependent on the composition of the deposited layer and demonstrates a nonlinear dependence. The system evolves to a stable composition that is controlled by the thermal budget and the rare earth content of the layer. It is shown that silicate formation can lead to a severe overe...

Miscibility of amorphous ZrO2–Al2O3 binary alloy

Miscibility is a key factor for maintaining the homogeneity of the amorphous structure in a ZrO2–Al2O3 binary alloy high-k dielectric layer. In the present work, a ZrO2/Al2O3 laminate thin layer has been prepared by atomic layer chemical vapor deposition on a Si (100) wafer. This layer, with artificially induced inhomogeneity (lamination), enables one to study the change in homogeneity of the amorphous phase in the ZrO2/Al2O3 system during annealing. High temperature grazing incidence x-ray diffraction (HT-XRD) was used to investigate the change in intensity of the constructive interference peak of the x-ray beams which are reflected from the interfaces of ZrO2/Al2O3 laminae. The HT-XRD spectra show that the intensity of the peak decreases with an increase in the anneal temperature, and at 800 °C, the peak disappears. The same samples were annealed by a rapid thermal process (RTP) at temperatures between 700 and 1000 °C for 60 s. Room temperature XRD of the RTP annealed samples shows a similar decrease in...

Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D nand Flash Memory

A vertical cylindrical SONOS cell with a novel bilayer polysilicon channel down to 22-nm diameter for 3-D NAND Flash memory is successfully developed. We introduce a thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole, after which it serves as the first layer of the bilayer polysilicon channel. This approach enables the 3-D architecture to achieve minimum cell area (4F2, with F being the feature size) without the need for the so-called pipeline connections. The smallest functional cells have the memory hole diameter F = 45 nm, resulting in 22-nm channel diameter. In case 16 cells are stacked, F = 45 nm would correspond to an equivalent 11-nm planar cell technology node. Excellent program/erase and retention obtained with the all-deposited ONO stack are demonstrated.

Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths

We demonstrate for the first time the scalability of NiSi and Ni/sub 3/Si FUSI gate processes down to 30 nm gate lengths, with linewidth independent phase and V/sub t/ control. We show that 1-step FUSI is inadequate for NiSi FUSI gates, because it results in incomplete silicidation at low thermal budgets or in a linewidth dependent Ni silicide phase - inducing V/sub t/ shifts - at higher thermal budgets. We show that V/sub t/ and WF shifts are larger on high-K (HfO/sub 2/ (250 mV) or HfSiON (330mV)) than on SiON (110mV) and report Fermi level unpinning for Ni-rich FUSI on high-K. In contrast, we demonstrate the scalability of Ni/sub 3/Si FUSI, with no phase control issues, and report HfSiON Ni/sub 3/Si FUSI PMOS devices with V/sub t/= -0.33 V. Lastly, we show that, for NiSi, phase control down to narrow gate lengths can be obtained with a 2-step FUSI process.

Thermal stability of dysprosium scandate thin films

The thermal stability of DyScO3 thin films in contact with SiO2 or HfO2 during annealing up to 1000°C has been studied. It is found that DyScO3∕SiO2 stacks react during annealing and a phase separation into polycrystalline Sc-rich (and relatively Si-poor) DySc silicate on top of an amorphous Dy-rich DySc silicate is observed. In contrast, DyScO3 is found to be thermodynamically stable in contact with HfO2 and to recrystallize upon annealing. These results demonstrate that the previously reported high crystallization temperature of >1000°C for DyScO3 is not an intrinsic material property but caused by silicate formation.