O. Zouraraki

Enabling Tb/s Photonic Routing: Development of Advanced Hybrid Integrated Photonic Devices to Realize High-Speed, All-Optical Packet Switching

We present recent advances in photonic integration introduced by integration-related European research project IST-MUFINS. The contribution of the project in the progress of a functional photonic integration is outlined, from device fabrication to device application focusing on photonic routing using multielement photonic chips. Specifically, we report on the transition from single-element to multielement photonic devices with the fabrication of hybrid integrated arrays of optical switches exploiting and upgrading the silica-on-silicon hybrid photonic integration. We demonstrate how the enhanced processing power and capacity of these components can be exploited to implement key functionalities required in next-generation fully integrated terabits per second photonic routers.

Photonics in switching: enabling technologies and subsystem design

This paper describes recent research activities and results in the area of photonic switching carried out within the framework of the EU-funded e-Photon/ONe+ network of excellence, Virtual Department on Optical Switching. Technology aspects of photonics in switching and, in particular, recent advances in wavelength conversion, ring resonators, and packet switching and processing subsystems are presented as the building blocks for the implementation of a high-performance router for the next-generation Internet.

Compact all-optical packet clock and data recovery circuit using generic integrated MZI switches

We present and evaluate a compact, all-optical Clock and Data Recovery (CDR) circuit based on integrated Mach Zehnder interferometric switches. Successful operation for short packet-mode traffic of variable length and phase alignment is demonstrated. The acquired clock signal rises within 2 bits and decays within 15 bits, irrespective of packet length and phase. Error-free operation is demonstrated at 10 Gb/s.

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We demonstrate an optically controlled 2times2 exchange/bypass switch using 0.8 m of highly nonlinear bismuth oxide fiber in an ultrafast-nonlinear-interferometer configuration. The switch has operated error-free with 10- and 40-Gb/s input signals, with power penalties in its bypass and exchange states of less than 0.3 and 1 dB, respectively. Use of the short bismuth oxide fiber ensured compact size, small latency, and improved operational stability compared to previous fiber-based switches

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We demonstrate a wavelength-converter-based optical time-slot-interchanger. It consists of three cascaded programmable delay stages and employs the first hybrid integrated, on a chip, quadruple array of semiconductor optical amplifier Mach-Zehnder interferometer switches. It exhibits error-free operation with 10-Gb/s nonreturn-to-zero packets and a power penalty of 1.8 dB.

2 Exchange/Bypass Switch Using 0.8 m of Highly Nonlinear Bismuth Oxide Fiber

We demonstrate an all-optical label/payload separation circuit implemented with hybridly integrated semiconductor-optical-amplifier-based Mach-Zehnder switches. It is shown to operate error-free with 40-Gb/s variable length data packets containing 27-1 pseudorandom bit sequence and short guardbands between them. The circuit requires only the data packets as input and its complexity does not increase with label length

Implementation of an All-Optical Time-Slot-Interchanger Architecture

We demonstrate an optical clock recovery circuit that extracts the line rate component on a per packet basis from short data packets at 40Gb/s. The circuit comprises a Fabry-Perot filter followed by a novel power limiting configuration, which in turn consists of a 5m highly nonlinear bismuth oxide fiber in cascade with an optical bandpass filter. Both experimental and simulation-based results are in close agreement and reveal that the proposed circuit acquires the timing information within only a small number of bits, yielding a packet clock for every respective data packet. Moreover, we investigate theoretically the scaling laws for the parameters of the circuit for operation beyond 40 Gb/s and present simulation results showing successful packet clock extraction for 160 Gb/s data packets. Finally, the circuits potential for operation at 320 Gb/s is discussed, indicating that ultrafast packet clock recovery should be in principle feasible by exploiting the passive structure of the device and the fsec-scale nonlinear response of the optical fiber.

All-Optical Label/Payload Separation at 40 Gb/s

We propose and demonstrate a wavelength converter-based time-slot-interchanger architecture consisting of cascaded programmable delay stages. It uses an integrated quadruple switch array of HMZI switches and operated error-free with 10 Gb/s NRZ packets.

Packet clock recovery using a bismuth oxide fiber-based optical power limiter

We present for the first time a quadruple array of MZI switches hybrid integrated on a single chip and package used to perform error-free clock, data recovery and label extraction for 40 Gb/s packets.

Optically-Addressable Packet Timeslot Interchanger Using a Quadruple Switch Array

We demonstrate an all-optical, self-synchronization scheme for optical packet switched network nodes. It provides both the packet clock signal and the packet beginning, marker pulse. The circuit uses two hybridly integrated MZI switches and has been evaluated with synchronous, asynchronous and variable length, data packets at 10 Gb/s. It is compact and requires relatively low energies to operate.