Octavio Maroto Santana

Determinant factors of leverage: An empirical analysis of Spanish corporations

Purpose – To contrast the different factors that can determine the level of debt of firms by means of panel data methodology. Design/methodology/approach – The variables used in the study are: size, generated resources, level of warrants, debt cost, growth opportunities, and reputation. Six hypotheses are considered. Findings – The results obtained suggest that the stated variables, other than reputation, can be considered to be explanatory variables of firm debt level. Using within-groups estimation and generalized least squares, the results suggest that the behavior of the sample throughout the study period is consistent with the fixed effects approach, in which the specific characteristics of each firm remain constant throughout time. Moreover, with respect to the six considered hypotheses, the analysis shows the influence of all stated variables except reputation on the leverage. Originality/value – Adds to the body of research that has focused on the analysis of the financial decisions of the firm, with the level of debt appearing as a relevant factor in explaining the relationship between investment and financing decisions.

A Low Power 2.5 Gbps 1:32 Deserializer in SiGe BiCMOS Technology

In this paper, the implementation of a 2.5 Gbps 1:32 deserializer in SiGe BiCMOS technology using standard cells and ECL bipolar circuits in order to minimize power consumption, is presented. The deserializer is composed of two main circuits: a demultiplexer and a clock distribution network. The architecture of the demultiplexer is based on a tree structure which allows using CMOS technology for low-speed stages. Clock signals are generated by the clock distribution network which is formed by static frequency dividers. In order to adapt both logic families, an ECL to CMOS converter was designed. High-speed ECL circuits were implemented full-custom with Cadence Virtuoso whereas standard cells were used for CMOS circuits were designed with Silicon Ensemble. Functionality has been verified through post-layout simulations performed in all technologys corner cases. The final IC has an area of 700 mum times 1045 mum and a total power consumption of 300 mW approximation

A 900 MHz Multiphase LC Oscillator with Sinusoidal Outputs in SiGe Technology

In this paper, the implementation of a 900 MHz multiphase oscillator with sinusoidal outputs in SiGe technology is presented. The circuit is based on a differential cross-coupled topology formed by four differential LC-oscillators that provide eight output signals with 45deg phase differences. The whole circuit was implemented full-custom. The final IC has an area of 1238 mum times 1238 mum and a total power consumption of 75 mW.

A novel gigabit multidrop serial link for high-speed digital systems

A multidrop backplane based on point-to-multipoint serial links enables interconnection between line cards without requiring a central switch fabric. However, maximum data rate in todays available multidrop serial links is limited to 400Mbps due to signal integrity concerns. In this paper, a novel gigabit multidrop serial link configuration for high-speed digital systems based on broadband power splitters with matching trace impedance, is proposed. Experimental results obtained from implemented prototypes demonstrate a satisfactory operation of the proposed multidrop serial backplane for a data rate of 3.5Gbps.