R. Esper-Chain

Round-trip delay effect on iterative request-grant-accept scheduling algorithms for virtual output queue switches

Virtual output queue (VOQ) is an efficient architecture for high-speed switches because it combines the low cost of input-queuing with high performance of output-queuing. The achievable throughput and delay performance heavily depends on the scheduling algorithm used to resolve the contention for the same output ports in each cell slot. Most VOQ scheduling algorithms, as exemplified by PIM and iSLIP, re based on parallel and iterative request-grant-accept arbitration schemes. Conventional performance evaluation of these scheduling algorithms, does not consider the effect of some issues inherent to their implementation on a modular and scalable VOQ switch with input ports and switch matrix residing on separate cards. One of the main issues is the Round-Trip Delay (RTD), defined as the latency between a connection is requested to the switch matrix card and the associated acceptance notification is received on the input port card. In this paper, the effect of RTD on performance parameters for PIM and iSLIP algorithms is presented, not being considered in deep in previous works appearing In the literature. Based on simulation results, RTD is demonstrated to affect significantly contention on output ports and mean queuing delay, and thus degrade the performance of cell-based VOQ switches.

Configurable Quadrant Photodetector: An Improved Position Sensitive Device

Position sensitive detectors (PSDs), used in high-end biotechnology, are based on optical sensors built over quadrant photodetectors (QPDs) or active pixel sensor (APS). These devices are intended to measure slight movements of laser spots. The QPD are, by far, the best approach in terms of resolution and noise, but requires complex and expensive x-y micropositioners to perform sensor alignment with the incoming laser spot. The APSs are more versatile devices that can virtually align with the spot by means of device configuration. However, due to its intrisic digital nature, the SNR and the resolutions are degraded in APS. In this paper, a new type of device called configurable QPD and its theory of operation is presented. This new device combines the analog operation of the QPD with the configurability of the APS, by means of combining photodetectors elements with analog switches in a matrix-shaped architecture. Finally, a prototype chip has been fabricated and tested and its measurements results are presented.

A Low Power 2.5 Gbps 1:32 Deserializer in SiGe BiCMOS Technology

In this paper, the implementation of a 2.5 Gbps 1:32 deserializer in SiGe BiCMOS technology using standard cells and ECL bipolar circuits in order to minimize power consumption, is presented. The deserializer is composed of two main circuits: a demultiplexer and a clock distribution network. The architecture of the demultiplexer is based on a tree structure which allows using CMOS technology for low-speed stages. Clock signals are generated by the clock distribution network which is formed by static frequency dividers. In order to adapt both logic families, an ECL to CMOS converter was designed. High-speed ECL circuits were implemented full-custom with Cadence Virtuoso whereas standard cells were used for CMOS circuits were designed with Silicon Ensemble. Functionality has been verified through post-layout simulations performed in all technologys corner cases. The final IC has an area of 700 mum times 1045 mum and a total power consumption of 300 mW approximation

A 600 MHz 2D-DCT processor for MPEG applications

In this paper we present the design of a 2D discrete cosine transform (2D-DCT) processor and its implementation using 0.6 /spl mu/m GaAs technology. The architecture of the processor, that resembles an FCT-MMM (fast cosine transform-matrix matrix multiplication) architecture, was development using distributed arithmetic (DA) in order to reduce the area required. The processor has about 50k transistors and occupies an area of 31.8 mm/sup 2/. It is able to process 400 Mpixels per second and at a clock frequency of 600 MHz, which is far beyond the requirements for real time high definition moving pictures in the MPEG-2 standard. Special consideration is given to the implementation of a transposition RAM which constitutes the bottleneck of the algorithm. A 64 word/spl times/12 bit, 1 ns access time transposition RAM was developed using a new dynamic RAM cell.

Hardware platform for wide-area vehicular sensor networks with mobile nodes

In recent years, Wireless Sensor Networks have experienced significant growth, mainly motivated by the development of standard communication protocols and the availability of low cost microcontrollers and wireless transceivers, resulting in low-power small-size sensing and data processing capable devices, and wireless communication links. In this paper, a hardware platform for the deployment of a heterogeneous multi-tiered Sensor Network architecture supporting highly mobile nodes covering wide geographic areas for automotive applications is proposed. In the presented network architecture, the low level system consists of an IEEE 802.15.4 based Wireless Sensor Network fully composed of compatible devices that support all the standard functionalities. As a novelty, some extensions are proposed to release part of the topological restrictions of IEEE 802.15.4 communication protocol which limit the development of WSN for applications with wide area coverage and high mobility requirements. The proposed hardware platform has been implemented and experimentally validated and characterized in vehicular applications to monitor and communicate specific environmental parameters in a heavy transport fleet.

Experimental gigabit multidrop serial backplane for high speed digital systems

Maximum data rate in todays available multidrop backplanes is limited to 400 Mbps due to signal integrity concerns. In this paper, an experimental gigabit multidrop serial backplane for high-speed digital systems based on a novel asymmetrical broadband power splitter configuration with matching trace impedance, is presented. Experimental results obtained from constructed prototype demonstrate a satisfactory operation of the proposed multidrop serial backplane for a data transfer rate of 3 Gbps.

GMDS: hardware implementation of novel real output queuing architecture

In this paper, a real output queuing switch prototype implementation is presented. This implementation is based on a novel high speed multidrop backplane and a general purpose line card which includes a Virtex-II 6000 FPGA. This switch is named GMDS (gigabit multidrop switch) and its main features are the switch matrix replacement by the multidrop backplane -increasing system reliability-, variable length packet switching support -avoiding bandwidth efficient loss-, multiple output queuing structure for supporting QoS (quality of service) and a minimum speedup.

Variable length packet scheduler algorithm with QoS support

A novel variable length packet scheduling algorithm focused on real output queue reference architecture is presented in this paper. The main features of this packet scheduler development are the Quality of Service (QoS) and variable length packet support. The packet scheduler supports up to eight traffic classes which can be assigned up to two different priorities. The bandwidth assigned to any traffic class is configurable. The packet scheduler has been described and simulated in C++ language under uniform and bursty traffic conditions.

Development and implementation of a configurable quadrant photodetector

Position sensitive detectors (PSDs), used in high-end biotechnology, are based on optical sensors built over quadrant photodetectors and active pixel sensors. These devices are intended to measure slight movements of a laser spot. Quadrant photodetectors (QD) are, by far, the best approach in terms of resolution and noise, but require complex and expensive micropositioning machinery to perform sensor alignment with the incoming laser spot. Active pixel sensors (APS) are more versatile devices that can virtually align with the spot by means of device configuration. However, due to its intrinsic digital nature, the SNR and resolutions are degraded in APS. In this article, a new type of device called configurable quadrant photodetector (CQD) is presented. It combines the analog operation of the QD with the configurability of the APS, by means of combining photodetector elements with analog switches in a matrix-shaped architecture. A prototype has been designed, fabricated, and tested, and its electrical characterisation is presented.

Wireless sensor network for wide-area high-mobility applications

In recent years, IEEE 802.15.4-based Wireless Sensor Networks (WSN) have experienced significant growth, mainly motivated by the standard features, such as small size oriented devices, low power consumption nodes, wireless communication links, and sensing and data processing capabilities. In this paper, the development, implementation and deployment of a novel fully compatible IEEE 802.15.4-based WSN architecture for applications operating over extended geographic regions with high node mobility support, is described. In addition, a practical system implementation of the proposed WSN architecture is presented and described for experimental validation and characterization purposes.