Phil Mawby

Low Stress Cycle Effect in IGBT Power Module Die-Attach Lifetime Modeling

Operational management for reliability of power electronic converters requires sensitive condition monitoring and accurate lifetime modeling. This study adds to the second aspect by examining the effect of cyclic junction temperature variations ΔTj of low amplitude in different stages of the power module ageing process. It is found that such relatively minor stress cycles, which happen frequently during normal operation, may not be able to directly initiate a crack but can contribute to the development of damage due to stress concentration. This agrees with the observation that the ageing process tends to accelerate toward the end of life. This study investigates the dependence of the ageing effect on the amplitude of ΔTj, the mean junction temperature T,,,, and the present health condition of the module, and proposes a lifetime model focusing on die-attach solder fatigue. It is assumed that the future-ageing process is independent of the operational history that has led to the current state of health. The model is intended for operational management of converter systems that are subjected to frequent low ΔTj stress cycles and are supposed to be in service reliably for a long time with a slow ageing process. Experimental results validate the model.

Characterization of the static and dynamic behavior of a SiC BJT

Silicon carbide (SiC) bipolar junction transistors (BJTs) are interesting candidates for high temperature and for high power applications primarily due to their low conduction losses and fast switching capability. The aim of this paper is to test and evaluate both the static and dynamic characteristics of SiC bipolar junction transistor (developed by TranSiC) rated at 600 V and 6 A at different temperatures. The high power curve tracer 371B has been used to test the DC output characteristics of the device in a temperature range of - 40degC to 175degC. A single pulse switching inductive load circuit has been used to test the dynamic characteristics of the SiC BJT. The experimental results with a normal gate drive circuit, show that the device has a turn on time of less than 0.5 mus and turn off time of less than 0.35 mus under test condition of 300 V, 10 A in an ambient temperature of range - 40degC to 125degC. In addition, the experimental data were analyzed to obtain the device performance parameters like the turn on, off time, transistor gain and switching losses.

Simulations of a Lateral PiN Diode on Si/SiC Substrate for High Temperature Applications

Simulations are presented of a lateral PiN power diode on a Si/SiC substrate for harsh environment, high temperature applications. Thermal simulations compare the Si/SiC solution to SOI, Si/SiO2/SiC, bulk Si and SiC, showing that the Si/SiC architecture, with its thin Si film intimately formed on SiC, displays significant thermal advantages over any other Si solution, and is comparable to bulk SiC. Detailed electrical simulations show that in comparison to the same device in SOI, a Si/SiC PiN diode offers no deterioration of the on-state performance, improved self-heating effects at increased current and can potentially support higher breakdown voltages.

4H-SiC Diode Avalanche Breakdown Voltage Estimation by Simulation and Junction Termination Extension Analysis

This paper presents and compares different avalanche breakdown voltage estimation methods in 4H-SiC (silicon carbide) using finite element simulation results on Schottky diode. 4H-SiC avalanche breakdown voltage and depletion width estimated with Baligas equations have shown to be higher than other estimation techniques and simulation results, especially for voltages higher than 5kV. This paper discusses the impact of choosing different junction termination extension (JTE) structures on two-dimensional junction curvature effects and electric field crowding for Schottky diodes Space-Modulated JTE (SMJTE) structure with optimum JTE dose and dimension could achieve up to 90% of the parallel plane breakdown voltage. For ultra high voltage devices (>15 kV) the SMJTE has significant improvement in terms of breakdown voltage. It also has a wider optimum JTE dose window. For 1 kV device there is not a significant difference in breakdown voltage between JTE and SMJTE structures.

Degradation and Reliability of Bare Dies Operated up to 300°C

In this paper, we demonstrate the degradation of commercially available 1.2kV SiC MOSFET bare dies subjected to long periods of isothermal heating at 300°C in air. Periodic electrical measurements indicated an increase in on-state resistance to different extents for three different vendor designs, and the discovery of a progressive rectifying type forward characteristic at low drain-source voltages. Subsequent investigations to determine the cause of the degraded electrical characteristics including sectioning and SEM/TEM analysis revealed some mechanical degradation within the device gate-source cross-sections and backside drain contact metal layers. While one vendor device was severely degraded after approximately 24 hours of heating, another vendor device was only just beginning to degrade after 100 hours, indicating that these devices may be used successfully in real applications at 300°C junction temperatures for relatively long periods.

Super-junction trench MOSFETs for improved energy conversion efficiency

Super-junction trench MOSFETs with ion-implanted pcolumns have been fabricated alongside conventional trench MOSFETs and are characterized by inductive switching circuits. The super-junction MOSFETs are designed to be on-state resistance (RDSON) matched with the conventional trench MOSFETs (using different die sizes). Another set of super-junction MOSFETs are fabricated with the same die area and are fitted in identical TO-220 packages. In the case of the RDSON matched devices, switching losses in the super-junction MOSFET were reduced by more than 55% whereas in the area matched devices, conduction losses were reduced by more than 50% in the super-junction MOSFETs. Using the principle of charge balance formed by very simple fabrication techniques, energy conversion efficiency has significantly been improved in power semiconductor devices.

Study of breakdown characteristics of 4H-SiC Schottky diode with improved 2-step mesa junction termination extension

The 4H-SiC Schottky diode with 2-step mesa junction termination extension (JTE) structure has been investigated and optimized using SILVACO device simulator. Comparisons between different JTE structures of breakdown voltage and electric field crowding for Schottky diodes have been made. Simulation results show that the Space Modulated two-zone JTE has the highest breakdown voltage which is about 97% of the ideal 1D parallel plane conditions. With the novel 2-step MESA Single Implant JTE, the breakdown voltage could achieve the same as the parallel plane breakdown votlage. The influences of the surface charge (Qs) and the oxide passivation on the breakdown characteristics of 4H-SiC Schottky diode with JTE are also investigated. A reduced sensitivity of breakdown voltage with respect to P-implant doping concentration is obtained for a novel 2-step mesa JTE with an additional P-type guard ring.

Compact electrothermal models for unbalanced parallel conducting Si-IGBTs

For high current applications, silicon IGBTs are normally connected in parallel to deliver the required current ratings. The devices are normally designed to have identical electrothermal parameters for equal current and power sharing. However, over the mission profile of the device, non-uniform degradation of the electro-thermal properties like solder delamination or gate contact resistance as well as unequal heat extraction from the heat sink, can cause the parallel connected IGBTs to have different electrothermal properties. In this paper, a compact and accurate electro-thermal model for parallel connected IGBTs has been developed and validated by experimental measurements.

Investigation of parasitic turn-ON in silicon IGBT and Silicon Carbide MOSFET devices: A technology evaluation

This paper investigates the switching rate and temperature dependence of parasitic (false) turn-on of power transistors when switched in power converters implemented in silicon IGBTs and Silicon Carbide (SiC) MOSFETs. It is shown that although high switching rates are normally desirable for minimizing the switching losses, this can result in shoot-through arm currents due to the combination of a Miller capacitance and high dV/dt. The power losses arising from this can be significantly larger than the normal switching losses since the device will still be blocking a considerable voltage. Even though SiC MOSFETs have a significantly smaller Miller capacitance compared with silicon IGBTs, this problem is no less of an issue due to higher switching speeds and lower threshold voltages. Additionally it is seen that the overshoot current increases with temperatures due to the negative temperature coefficient of the threshold voltage in both device technologies. Various solutions to overcome this have been analyzed for both device technologies. It is seen that the effectiveness of the mitigation techniques differs, and in general due to the lower threshold voltage of the SiC device, the solutions proposed are less effective.

Advancements in SiC Power Devices Using Novel Interface Passivation Processes

For the next generation 4H-SiC MOSFET devices it is very critical to have a good 4H-SiC/SiO2 interface. In this paper we reported two new passivation processes - thin phosphorous (P) passivation and nitrogen plasma (N2P) passivation. With thin P passivation the mobility of ~75 cm2/V·s can be achieved with improved threshold voltage stability. N2P passivation gives an alternative to introduce nitrogen (N) at the interface in minimum oxygen (O) ambient during passivation. With this new N2P process we can introduce more N at the interface, almost two times compared to standard NO (nitric oxide) passivation.