Olivier Fourquin

A 9-pJ/Pulse 1.42-Vpp OOK CMOS UWB Pulse Generator for the 3.1–10.6-GHz FCC Band

This paper presents the design of a fully integrated ultra-wideband (UWB) pulse generator for the Federal Communications Commission (FCC) 3.1-10.6-GHz band. This generator is reserved for medium rate applications and achieves pulses for an on-off keying (OOK) modulation, pulse position modulation, or pulse interval modulation. This UWB transmitter is based on the impulse response filter method, which uses an edge combiner in order to excite an integrated bandpass filter. The circuit has been integrated in an ST-Microelectronics CMOS 0.13-¿m technology with 1.2-V supply voltage and the die size is 0.54 mm2. The pulse generator power consumption is 9 pJ per pulse and achieves a peak to peak magnitude of 1.42 V. The pulse is FCC compliant and the generator can be used with a rate up to 38 Mbs-1 with an OOK modulation. Based on the FCC power spectral density limitation, a sizing method is also presented.

Double-Quadrature UWB Receiver for Wide-Range Localization Applications With Sub-cm Ranging Precision

The interest of industry for localization technologies is growing, because of their ability to allow a wide variety of applications. Among the different technologies, UWB is known to potentially offer the best precision. This paper presents a fully integrated low-power UWB impulse radio receiver dedicated to communication and ranging applications. The new architecture based on double quadrature is used to reach sub-cm ranging precision while limiting the speed requirements and complexity of ADC and digital signal processing. Much attention has been paid to rejecting the out-of-band signals which could degrade receiver performance while fully exploiting the available spectrum in the [3-5 GHz] band. The 5.8-mm2 0.13- μm CMOS receiver consumes 50 mW at 50-Mb/s maximum data rate. It shows -95-dBm sensitivity at 1 Mb/s and 2.5-mm maximum ranging error at 10 m.

Fully tunable UWB pulse generator with zero DC power consumption

The design of a fully tunable pulse generator using only logic cells is presented and simulated with 0.13µm standard CMOS process. The generator is based on the elementary pulse combination and can synthesize different UWB pulse shapes. The generator uses logic gates to achieve the elementary pulses and a H-bridge to make the combination which leads to a zero DC power consumption. To achieve FCC compliant pulse having 2VPP magnitude the generator consumes 140 pJ by pulse using 1.2V supply voltage.

A remotely UHF powered UWB transmitter for high precision localization of RFID tag

The design of a remotely UHF powered UWB transmitter is presented in 0.13µm CMOS standard process. Power harvesting unit is based on a Dickson voltage multiplier and UWB pulse generator uses filtered combined edge method. Multi-Vt technique and CMOS logic allows pulse generator power consumption between two consecutive pulses to be reduced enough to be remotely powered. It achieves FCC compliant pulses having 1.82Vpp and a PRF of 15kHz at 10m thanks to the power harvesting unit.

Low-power CMOS energy detector for noncoherent impulse-radio UWB receivers

A low power CMOS energy detector for 3.1–10.6 GHz non-coherent impulse-radio UWB receivers is implemented in a 0.13 µm CMOS process. The detector architecture is based on a squarer circuit realized with MOS transistors biased in the sub-threshold region. The squared signal is integrated using a low pass amplifier that allows the receiver gain to be optimized. A comparator with a tunable threshold is then used as a decision circuit. Experimental results show that a BER of 10− is achieved for a peak-to-peak voltage of 140 mV at the detector input at 200 Mb/s data rate. Assuming that the detector is driven by a LNA of gain 22 dB, leads to a receiver sensitivity of −45 dBm. The receiver dissipates only 25 mW, corresponding to an energy efficiency of 0.13 nJ/bit and the chip occupies 0.7 mm2.

CMOS UWB pulse generator co-designed with package transition

The design of an UWB pulse generator is presented in the context of low cost applications. The pulse generator is fully integrated in a 0.13 μm CMOS technology and achieves 1Vpp magnitude pulses with only 2.25pJ of energy consumed by pulse and 1.2V voltage supply. The generation method used in this design is well suited for packaged IC using wire bond interconnections. Tow methods of interconnection are presented. It is shown that a co-design of the generator with the package transition can preserve the signal integrity while increasing the pulse magnitude up to 1.4Vpp with the same power budget.

Low-power clock and data recovery circuit for IR-UWB receiver power management

A low power clock and data recovery (CDR) for low data rate applications is presented. The CDR circuit, implemented as a phase locked-loop (PLL), deals with very narrow pulses from an energy detector in a non-coherent Impulse Radio based Ultra Wide Band (IR-UWB) receiver. To considerably reduce the power consumption of such a receiver, the proposed circuit is intended to be used to turn off analog/RF blocks between detected pulses. For that, a modified Hogge-type phase detector (PD) is proposed that enables the PLL to efficiently work with “return-to-zero (RZ) low duty cycle” (UWB pulses) input data. A simple pre-charge circuit is added to reduce the PLL lock time. The circuit has been realized in a 0.13 μm CMOS technology. Process variations taken into account through corner simulations show that the loop locks for all corners. Post-layout simulations at typical corner parameters show a power consumption of only 16 μW, a lock time of 130 μs and a recovered clock peak-to-peak jitter of 25 ns (2.5% UI) for an input data rate of 1 Mb/s.

A 4GHz CMOS 130 nm IR-UWB dual front-end transceiver for IEEE802.15 standards

A single chip CMOS 130 nm transceiver for UWB-IR communications was assembled and measured for further integration into a demonstrator aiming compatibility with the recently published IEEE802.15.6 standard for Body Area Networks. The transmitter achieves a 10.9 mA current consumption for the 15.6MHz pulse repetition frequency and 1.5V peak-to-peak voltage. The receiver is an innovative combination of a low current consumption non coherent envelop detector and of a high sensitivity coherent quadrature demodulator. Different compromises in sensitivity, current consumption and acquisition speed are made possible. This paper briefly describes the architecture and provides the chip measurement results.

Enhanced wire bond transition from die to chip carrier for 3.1-10.6 GHz UWB applications

We present in this paper a way to optimize the bandwidth of standard wire bond (WB) transition from die to chip carrier. This optimization is based on a simple lumped model of the WB transition taking into account the common ground impedance between the die and the chip carrier levels. The model also includes the magnetic coupling between the signal WB and the grounds WB. This model is validated by full wave electromagnetic simulations. On the basis of this lumped model simple guiding rules to increase the transition bandwidth are given. The signal integrity of the WB transition is enhanced and a return loss greater than 15 dB is obtained in the 3.1-10.6 GHz frequency band with standard WB lengths.

Chip-Package co-design of 10 GHz bandwidth low noise active front-end interface

We present in this paper the design of a 10 GHz bandwidth low noise active front end interface. This interface uses a common gate amplifier architecture co-designed with the carrier to die bonding wire transition. The carrier to die transition is used to build a low loss third order low pass filter which is used as input matching cell for the common gate amplifier. This Chip-Package interface allows low fabrication cost because it uses standard bonding wires and low silicon area. The proposed Chip-Package interface is used to design a 3.1–10.6 GHz UWB LNA in a 0.13µm CMOS technology. The simulated results show a return loss greater than 10 dB with a noise figure lower than 4.5 dB in the 3.1–10.6 GHz UWB FCC frequency range with a power consumption of 8.6 mW and a silicon area of 0.2 mm2.