Olivier Pasquier

A generic RTOS model for real-time systems simulation with systemC

The main difficulties in designing real-time systems are related to time constraints: if an action is performed too late, it is considered as a fault (with different levels of criticism). Designers need to use a solution that fully supports timing constraints and enables them to simulate early on the design process a real-time system. One of the main difficulties in designing HW/SW systems resides in studying the effect of serializing tasks on processors running a real-time operating system (RTOS). In this paper, we present a generic model of RTOS based on systemC. It allows assessing real-time performances and the influence of scheduling according to RTOS properties such as scheduling policy, context-switch time and scheduling latency.

Performance Monitoring and Assessment of Embedded HW/SW Systems

Performance assessment of embedded HW/SW systems built with various types of VLSI components, i.e. heterogeneous multi-processor architectures, is important to help the development of complex real-time applications. To design such a tool, two issues must be solved: the gathering of relevant information simultaneously on several components without disturbing the application behavior, display of the performance results in a way that can be easily interpreted by designers. This paper presents a significant solution for the two above issues. We first describe what the goal for designers is and what kind of applications are concerned. Then we describe the principle of collecting an event trace and the technique to evaluate the selected performance indexes. The monitoring technique, based on a specific ASIC, is non-intrusive and allows our tool to capture real-time event occurrences from software tasks, and even from hardware functions implemented in ASICs. Each event is automatically time-stamped, collected and processed in real-time to evaluate the performance indexes selected by the designer. We also describe the display tool which clearly shows the results to the designer according to different representations. This technique and the associate real-time performance analyzer are integrated in a complete development process based on the MCSE methodology.

Performance assessment of embedded Hw/Sw systems

Performance assessment of embedded Hw/Sw systems built with various types of VLSI components, i.e. heterogeneous multi-processor architectures, is important to help the development of complex real-time applications. To design such a tool, two issues are to be solved, relevant information gathered simultaneously on several components without disturbing the application behavior, and the display of the performance results in a way which is easily interpreted by designers. This paper presents an interesting solution for the two above issues. We first describe what the goal for designers is and what kind of applications are concerned. Then we describe the principle of collecting an event trace and the technique to evaluate the selected performance indexes. The monitoring technique, based on a specific ASIC, is nonintrusive and allows to capture real-time event occurrences from software tasks and even from hardware functions implemented in ASICs. Each event is automatically time-stamped, collected and processed in real-time to evaluate the performance indexes selected by the designer. We also describe the display tool which clearly shows to the designer the results according to different representations. This technique and the associated real-time performance analyzer are integrated in a whole development process based on the MCSE methodology.

Uninterpreted co-simulation for performance evaluation of Hw/Sw systems

Performance modeling and evaluation of embedded hardware/software systems is important to help the CoDesign process. The hardware/software partitioning needs to be evaluated before synthesizing the solution. This paper presents a co-simulation technique based on the use of an uninterpreted model able to accurately represent the behavior of the whole system. The performance model includes two complementary viewpoints: the structural viewpoint which describes the functional structure, the hardware structure, the functional to hardware mapping, and the behavioral viewpoint which specifies the temporal evolution of each function or process. Attributes are added to the graphical model to specify the local properties of all components. The performance properties of the solution are obtained by simulation with VHDL. Software functions are executed according to the availability of an execution resource which simulates a microprocessor. This technique leads to rapidly obtain a lot of results by modifying appropriate parameters of the model, and so to easily scan the CoDesign space to decide on the best implementation. This modeling and estimation technique is fully integrated in a whole development process based on the MCSE methodology.

An object-based executable model for simulation of real-time Hw/Sw systems

This paper describes a simulation technique for real-time Hw/Sw systems based on an object executable model. It allows designers to seamlessly estimate and verify their solutions from a high-level functional description to a Hw/Sw partitioned design. The same model, enhanced with algorithms, can be used to simulate interpreted models in order to observe the behavior of a whole system and its environment, as well as uninterpreted models which are useful for performance estimation and so help Hw/Sw partitioning. Our (co-)simulation technique is based on the translation of a high level model of the application into a C++ program which uses a library of predefined classes. While running, the program produces an event trace, the contents of which can be set by the user. This technique allows us to quickly analyze the influence of application or architecture parameters on the application behavior.

Real-time behavior monitoring for multi-processor systems

Abstract Monitoring tools to observe the behavior of multi-task programs running on multi-processor architectures are important to help debugging complex real-time applications. To design such a tool, two issues are to be solved, relevant information gathering without disturbing the application behavior, display of this information in a way easily interpreted by designers. This paper presents a new solution for these two above issues. First, it describes a method and a tool to collect an event trace which can be implemented by software only or in an hybrid (software and hardware) way. Information to be collected are automatically selected from the tool and the overhead monitoring time is kept very low. Then, it describes the display tool which clearly shows to the designer the inter-function dependencies, all task states and execution times of real-time kernel primitives. This tool may also be used by designers to observe the value of relevant internal variables of the system. Our solution is target independent: it can be implemented on multi-transputer systems or on any conventional or heterogeneous microprocessor architectures.

A system level model for software defined radio design

This paper presents a system level design approach for software defined radio (SDR) modeling. The proposed model aims at both taking into account the reconfiguration mechanisms and the processing functions of wireless applications. The benefits of our approach are illustrated through the design and the simulation of a reconfigurable modulation system

A state-based modeling approach for efficient performance evaluation of embedded system architectures at transaction level

Abstract models are necessary to assist system architects in the evaluation process of hardware/software architectures and to cope with the still increasing complexity of embedded systems. Efficient methods are required to create reliable models of system architectures and to allow early performance evaluation and fast exploration of the design space. In this paper, we present a specific transaction level modeling approach for performance evaluation of hardware/software architectures. This approach relies on a generic execution model that exhibits light modeling effort. Created models are used to evaluate by simulation expected processing and memory resources according to various architectures. The proposed execution model relies on a specific computation method defined to improve the simulation speed of transaction level models. The benefits of the proposed approach are highlighted through two case studies. The first case study is a didactic example illustrating themodeling approach. In this example, a simulation speed-up by a factor of 7,62 is achieved by using the proposed computation method. The second case study concerns the analysis of a communication receiver supporting part of the physical layer of the LTE protocol. In this case study, architecture exploration is led in order to improve the allocation of processing functions.

A programmable multi-language generator for CoDesign

This paper presents an innovative technique to efficiently develop hardware and software code generators. The specification model is first converted into its equivalent data structure. Target programs result from a set of transformation rules applied to the data structure. These rules are written in a textual form named Script. Moreover, transformations for a specific code generator are easier to describe because our solution uses a template of the required output as another input. The result is a meta-generator entirely written in Java. The concept and its implementation have been demonstrated by developing a C/WxWorks code generator, a behavioral VHDL generator, a synthesizable VHDL generator.

An interactive modeling and generation tool for the design of Hw/Sw systems

This paper addresses the design of nowadays embedded hardware and software systems. We propose an interactive tool enabling designers: to easily describe and configure system solutions at the functional and the architectural levels, to interactively define properties for all internal components, to incrementally generate executable code programs for both hardware and software components. The basis of our approach is the MCSE methodology which specifies the description model and the method designers can follow to develop Hw/Sw solutions. The graphical model useful for system-level description includes the functional structure, behaviors of components, the physical architecture, the functional/spl rarr/architecture mapping after Hw/Sw partitioning. Our model also includes the concept of attribute to specify standard and user-defined properties for all components. These attributes are interactively edited and they directly drive a set of code generators, each one focussing a specific target (C with WxWorks, synthesizable VHDL, Hw/Sw interface, C++).