Sébastien Le Nours

A state-based modeling approach for efficient performance evaluation of embedded system architectures at transaction level

Abstract models are necessary to assist system architects in the evaluation process of hardware/software architectures and to cope with the still increasing complexity of embedded systems. Efficient methods are required to create reliable models of system architectures and to allow early performance evaluation and fast exploration of the design space. In this paper, we present a specific transaction level modeling approach for performance evaluation of hardware/software architectures. This approach relies on a generic execution model that exhibits light modeling effort. Created models are used to evaluate by simulation expected processing and memory resources according to various architectures. The proposed execution model relies on a specific computation method defined to improve the simulation speed of transaction level models. The benefits of the proposed approach are highlighted through two case studies. The first case study is a didactic example illustrating themodeling approach. In this example, a simulation speed-up by a factor of 7,62 is achieved by using the proposed computation method. The second case study concerns the analysis of a communication receiver supporting part of the physical layer of the LTE protocol. In this case study, architecture exploration is led in order to improve the allocation of processing functions.

A dynamic computation method for fast and accurate performance evaluation of multi-core architectures

Early estimation of performance has become necessary to facilitate design of complex multi-core architectures. Performance evaluation based on extensive simulations is time consuming and needs to be improved to allow exploration of different architectures in acceptable time. In this paper, we propose a method that improves the tradeoff between simulation speed and accuracy in performance models of architectures. This method computes during model execution some of the synchronization instants involved in architecture evolution. It allows grouping and abstracting architecture processes and this way significantly reduces the number of simulation events. Experiments show significant benefits from the computation method on the simulation time. Especially, a simulation speed-up by a factor of 4 is achieved in the considered case study, with no loss of accuracy about estimation of processing resource usage. The proposed method has potential to support automatic generation of efficient architecture models.

A Case Study of Simulation and Performance Evaluationof a SDR Baseband Architecture

Application of Software Defined Radio (SDR) principles to mobile devices faces numerous opposing constraints including low power, low cost, and high performance. This situation motivates the definition of advanced methods, models, and tools in order to maintain the design complexity of terminal architectures. In this context, architects of next generation radio communication systems aim at designing SDR baseband architectures able to support a wide variety of communication interfaces with a wide range of processing resources and that fully meet expected requirements. As a result, it is mandatory to efficiently assist system architects in the process of evaluating performances of potential architectures and in exploration of the design space. In this paper, we present a case study representative of next generation radio communication systems and we describe its modeling and evaluation of performances of the related architecture. The case study corresponds to an adaptive multi-standard and multi-application radio communication system. Performance evaluation is performed following a simulation-based approach. Modeling techniques are proposed to facilitate estimation of expected resources according to complex use case scenarios and to allow achieving a good compromise between simulation speed of architecture models and accuracy of provided estimations. The presented results concern the evolution over time of the architecture and the observation of resource usage taking into account dynamic changes of the system environment.

A state-based modeling approach for fast performance evaluation of embedded system architectures

Abstract models are means to assist system architects in the evaluation process of hardware/software architectures and then to cope with the still increasing complexity of embedded systems. Efficient methods are necessary to correctly model system architectures and to make possible early performance evaluation and fast exploration of the design space. In this paper, we present the use of a specific modeling approach to improve evaluation of non-functional properties of embedded systems. The contribution is about a computation method defined to improve modeling of properties used for assessment of architecture performances. This method favors creation of abstract transaction level models and leads to significantly reducing simulation time but still preserving accuracy of results. The benefits of the proposed approach for evaluation of performances of system architectures are highlighted through analysis of two specific case studies.

Performance evaluation of an automotive distributed architecture based on HPAV communication protocol using a transaction level modeling approach

Due to increasing complexity of communication infrastructures in the automotive domain, reliable models are necessary in order to assist designers in the development process of networked embedded systems. In this context, transaction level modeling, supported by languages as SystemC, is a promising solution to assess performances of networked architectures with a good compromise between accuracy and simulation speed. This article presents the application of a specific modeling approach for performance evaluation of a networked embedded system inspired from the automotive domain. The considered approach is illustrated by the modeling of a video transmission system made of three electronic controller units and based on a specific power line communication protocol. The created model incorporates description of various communication layers and simulation of the model allows evaluation of time properties and memory cost inferred.

Performance evaluation of an automotive distributed architecture based on a high speed power line communication protocol using a transaction level modeling approach

With the increasing complexity of communication infrastructures in the automotive domain, approaches for modeling architectures at a high abstraction level have become mandatory to assist designers in the development process of such networked embedded systems. Simulation of architecture models, early in the design process, is also necessary to detect and fix errors and performance issues. In this context, transaction level modeling approaches, supported by languages like SystemC, represent promising solutions to allow performances of networked architectures to be assessed with a good compromise between accuracy and simulation speed. This article presents the application of a simulation-based approach for performance evaluation of a networked embedded system inspired by the automotive domain. The presented modeling approach is defined to efficiently capture the characteristics of architectures for real-time image processing applications. The originality of this paper concerns the considered case study which corresponds to the modeling of a video transmission system made of three electronic controller units and based on a specific power line communication protocol. Compared with traditional communication protocols used in the automotive domain, power line communication is considered here to improve integration of advanced real-time image processing applications. The created model incorporates the description of the different communication layers involved in the studied distributed architecture. Simulation of the model allows evaluating time properties of the architecture according to the various system parameters. Furthermore, the memory cost inferred is also evaluated. Architecture parameters can then be correctly tuned to fully meet the expected requirements.

A Hybrid Simulation Approach for Fast and Accurate Timing Analysis of Multi-Processor Platforms Considering Communication Resources Conflicts

In the early design phase of embedded systems, discrete-event simulation is extensively used to analyse time properties of hardware-software architectures. Improvement of simulation efficiency has become imperative for tackling the ever increasing complexity of multi-processor execution platforms. The fundamental limitation of current discrete-event simulators lies in the time-consuming context switching required in simulation of concurrent processes. In this paper, we present a new simulation approach that reduces the number of events managed by a simulator while preserving timing accuracy of hardware-software architecture models. The proposed simulation approach abstracts the simulated processes by an equivalent executable model which computes the synchronization instants with no involvement of the simulation kernel. To consider concurrent accesses to platform shared resources, a correction technique that adjusts the computed synchronization instants is proposed as well. The proposed simulation approach was experimentally validated with an industrial modeling and simulation framework and we estimated the potential benefits through various case studies. Compared to traditional lock-step simulation approaches, the proposed approach enables significant simulation speed-up with no loss of timing accuracy. A simulation speed-up by a factor of 14.5 was achieved with no loss of timing accuracy through experimentation with a system model made of 20 functions, two processors and shared communication resources. Application of the proposed approach to simulation of a communication receiver model led to a simulation speed-up by a factor of 4 with no loss of timing accuracy. The proposed simulation approach has potential to support automatic generation of efficient system models.

Transaction Level Modeling of a Networked Embedded System Based on a Power Line Communication Protocol

The increasing complexity of communication infrastructures in the automotive domain implies the use of reliable models to assist designers in the development process of networked embedded systems. In this context, transaction level modeling, supported by languages as SystemC, is a promising solution to assess performances of networked architectures with a good compromise between accuracy and simulation speed. This article presents the modeling and performance evaluation of a video transmission system supported by three electronic controller units and based on a specific power line communication protocol. The created model incorporates the various communication layers considered. The simulation of the model allows the evaluation of time properties and memory cost inferred.

A framework for the design of reconfigurable fault tolerant architectures

The rapid evolutions in reconfigurable electronic products design permit to handle more and more complex applications. New fields of investigations (i.e. automotive, aerospatial, banking,…) are interesting but require a high level of dependability. This paper proposes a framework to design reconfig-urable architecture supporting fault-tolerance mitigation scheme. The proposed framework allows simulation, validation of mitigation operations, but also to size architecture resources. The implementation of a fault-tolerant reconfigurable platform permits to validate the proposed model and the effectiveness of the framework. This implementation shows the potential of dynamically reconfigurable architectures for supporting fault-tolerance in embedded systems.