Olivier Tesson

Signal-power integrity and EMI analysis for singlechip and multi-chip-module applications

In this paper, a global Chip-Package-PCB Co-Design and Co-Verification methodology is successfully applied to Single-Chip Down-converter circuit and Multi-Chip-Module in transmit mode. Full-wave electromagnetic and thermal Co-Analysis approach is adopted to investigate impact of critical RF couplings, power dissipation and grounding strategies on systemlevel performances. The Single-Chip down-converter circuit shows 43dB conversion gain, with 6.5dB noise figure and output IP3 of 18dBm. The MCM design demonstrates 35dBm output IP3, 25dBm output CP1, with 45dB image rejection with 25dB voltage gain for a dissipated power of 2.2W.

High-Quality varactors and Schottky-Diodes in SiGe:C Technology for mm-Wave and THz applications

This paper presents the design and experimental characterization of High-Quality varactors and Schottky Diodes in SiGe:C Technology. A new layout topology for differential varactor is proposed to significantly improve its quality factor up to the Ka band. This new layout topology addresses the typical trade-off that designers often face between the quality factor and the tuning range. 2x improvement of the quality factor up to 30 GHz over conventional layout topology made of multi fingers is demonstrated. On the other side, special care has been taken to minimize parasitic capacitance between anodes to keep the tuning range stable. Measured VCO with this new type of varactor shows a reduction of 2 dB in the Phase Noise at 1 MHz from the carrier. Silicon-based Schottky Diodes arrays with Cut-Off frequencies in the THz domain are designed and fabricated. Concurrent optimization of Schottky Diode arrays geometry and electrical performances (Cutoff frequency, parasitic, Quality-factor, Sensitivity, Responsiveness, etc.) is carried out based on careful modeling and experimental characterizations. Analysis of the Schottky Diode arrays including sweep in DC-biasing conditions to control non-linearities is studied. Detection mechanisms related to the non-linear behavior are studied and figures of merit are introduced for their analysis.

Design of Lange Couplers with local ground references using SiGe BiCMOS technology for mm-Wave applications

SiGe BiCMOS design solutions for Lange Couplers operating in the mm-Wave domain are proposed. Various circuit topologies are designed, fabricated, and experimentally compared in terms of their RF performances. Effect of grounding strategies and influence of DTI pattering are studied both for CPS and CPW topologies to evaluate dependence of obtained RF performances on Die back-side grounding strategies. Perspectives for physics-based broadband equivalent circuit model extraction are proposed for lumped elements implementation of Lange Couplers using custom variation-aware RLC library elements.

Two Complementary Methods for Parasitic Coupling Reduction within MMIC's

This paper teaches the way to reduce parasitic couplings by using special device architecture together with optimized routing. Two main options are proposed in order to tackle parasitic coupling related issues: a low stray field monolithic inductor implementation and conformal Faraday cage shielding used for on chip interconnect lines. Both examples have been implemented on silicon and on-wafer two ports S-parameters measurements have been carried-out against frequency up to 50 GHz. It is shown that these structures can decrease parasitic coupling from 20 to 30 dB without any impact on application footprint. In case of interconnect lines, the proposed approach also allows saving area and optimizing routing. A compact modeling is proposed for the device inductor while a BBS (Broad Band Spice) extraction is performed for the micro coaxial lines. Both modeling approach are corroborated to measurements. Based on the available data, correlation is found satisfactory between measurements and electrical modeling. On the other side, we show experimentally that both proposed approaches allow reducing inductive crosstalk by at least 100 times or 20 dB

A low phase noise signal generation system for Ka-Band P2P applications based on an injection-locked frequency tripler

A signal generation system composed by a subharmonic VCO followed by an injection-locked frequency tripler (ILFT) is designed in a 0.25 μm BiCMOS SiGe:C technology. The ILFT implements a cascoded current-biased common emitter configuration that exploits the second harmonic of the VCO to enhance the efficiency in the generation of the injecting signal responsible for the ILFT locking. At 30.8GHz, the system achieves a phase noise of -112 dBc/Hz at 1 MHz offset. The total current consumption is 38 mA for a supply voltage of 2.5 V.

Analysis and Design of LC-Oscillators associated with Frequency Multipliers: A Phase Noise Perspective

Summary When a local oscillator signal generation system is based on an LC oscillator and a frequency multiplier, the question of determining the optimal multiplication factor is a key issue. In this paper, the problem is addressed in order to minimize the 1/f2 phase noise within a tuning range constraint. The analysis, with a practical graphical representation, reveals the oscillator phase noise dependence on the oscillating frequency in the transition from two different regimes, named the inductor-limited quality factor and the capacitor-limited quality factor. The results obtained enable the evaluation of the phase noise performance of systems based on a sub-harmonic and super-harmonic oscillators and how they compare with an oscillator in the fundamental mode. Crucial questions like the phase noise improvement that these systems can achieve are analytically answered. A design methodology is thus proposed and verified through measurements on a frequency source at 31 GHz, composed by a sub-harmonic voltage-controlled oscillator followed by an injection-locked frequency tripler, dedicated to backhauling applications, designed on a BiCMOS process technology. The tuning range is 10%, and the phase noise at a 1-MHz offset is −112 dBc/Hz. Copyright

A low phase noise tri-band LO generation for Ku and E band radios for backhauling Point-to-Point applications

This paper demonstrates a fully integrated tri-band LO generation system based a low phase noise 12 GHz sub-harmonic VCO and an injection locked frequency tripler (ILFT) as the signal source. The system generates simultaneously three outputs at f₀, f₀/2 and 2×f₀, with maximum frequency of 36 GHz, 18 GHz and 72 GHz respectively. The system which is implemented in a 0.25-μm SiGe:C BiCMOS technology, has a phase noise of -107.72 dBc/Hz at 1 MHz offset from the 36 GHz signal measured at the f₀-port. All outputs have a tuning range of 9.5% The in-band output power at the f₀, f₀/2 and 2×f₀ outputs is higher than 3 dBm, 0 dBm and -20 dBm respectively. The whole system draws 120 mA for a power supply of 2.5 V.

Design and characterization of an integrated microwave generator for BIST applications

This paper presents a circuit architecture for a new integrated on chip test method for microwave circuits. The proposed built-in-self-test (BIST) cell targets a direct low-cost measurement technique of the gain and the 1 dB input compression point (CP1) of a K-band satellite receiver in the 18–22 GHz frequency bandwidth. A signal generator at the radiofrequency (RF) front end input of the device under test (DUT) has been integrated on the same chip. To inject this RF signal, a loopback technique has been used and the design has been accommodated for it. This paper focuses on the design of the most sensitive block of the BIST circuit, i.e. the RF signal generator. This circuit, fabricated in a SIGe:C BiCMOS process, consumes 10 mA. It presents a dynamic power range of 17 dB (−41; −24 dBm) and operates in a frequency range of 5.6 GHz (17.5; 23 GHz). This BIST circuit gives new perspectives in terms of test strategy, cost reduction, and measurement accuracy for microwave-integrated circuits and could be adapted for mm-wave circuits.

Design of a K-band wideband controlled variable attenuator for microwave Built-In-Self-Test applications

This paper presents a new microwave wideband controlled variable attenuator designed in a BiCMOS process. This variable attenuator is implanted as part of a microwave Built-In-Self-Test (BIST) circuit. The proposed BIST cell is dedicated for direct low cost measurement of the gain and the input 1dB compression point (CP1) of a K-band satellite reception chain (18.2 GHz-22 GHz). The simulation of the controlled variable attenuator with RLCk parasitic extraction shows that it can operate up to 100 GHz with a consumption of 4 mA, an area less than 0.009 mm2 excluding pads and a gain range of 36 dB when the attenuator is alone and 17 dB when it is concatenated to the other blocks. This result was confirmed with the performed measurement on the BIST device. This BIST circuit gives new perspectives in term of test strategy, cost reduction and measurement accuracy for mm-wave integrated circuits.

Design of an embedded RF signal generator for BIST application

This paper presents the design of an RF test signal generator for a Built-In-Self-Test (BIST) application. This embedded generator is the most sensitive part of a new BIST architecture which basically, consists of integrating an RF generator at the RF Front End input and an RMS detector at the IF side on chip at lowest cost. The proposed BIST cell targets a direct low cost measurement of the gain and the input 1dB compression point (CP1) of a K-band satellite reception chain (18.2 GHz - 22 GHz). The BIST generator, designed in a BiCMOS process, consumes 10 mA. Its power range is equal to 17 dB [-45 dBm; -28 dBm] and its frequency varies from 17.5 GHz to 23.1 GHz. This BIST circuit provides new perspectives in terms of production test strategy, cost reduction and measurement accuracy for mm-wave integrated circuits.