Jean-Baptiste Begueret

Characterization of Si-based monolithic transformers with patterned ground shield

This paper investigates the impact of patterned ground shield on monolithic integrated transformers. The minimum insertion loss is shown to be a useful figure of merit. It is used to evaluate transformer performances. We demonstrate that the use of a patterned ground shield increases the quality factor of both primary and secondary coils. It increases also the mutual coupling coefficient and thus reduces the minimum insertion loss at high frequency, while at low frequency it has no effect. Measured insertion loss as low as 1.27dB at 5GHz, has been observed. The impact of patterned ground shield is shown to be more significant in the case of transformer with important transformation ratio

A Radiation-Hardened Injection Locked Oscillator Devoted to Radio-Frequency Applications

Implemented in a 0.25 mum SiGe technology, a 5.2 GHz Injection Locked Oscillator (ILO) for Radio-Frequency (RF) applications is shown to be intrinsically radiation-hardened. Design principles and laser-based testing results are presented

System design of bandpass sampling RF receivers

This paper presents a novel method for analyzing the analog specifications of bandpass sampling (BPS) receivers. The method guarantees fast convergence to the required performance and can be exploited to study the best configurations for a given constraint (eg. power, integration) using different noise degradation distributions. A wide-band system-level simulation tool which separately models each degradation source is developed to validate the method.

Delay oriented design methodology: application to the design of a VHF low power VLSI polyphase oscillator

A new design methodology (Delay Oriented Design-DOD) has been developed in order to design a novel oscillator architecture. A 250 MHz DOD oscillator has been implemented on a 0.8 /spl mu/m, two metal layers standard VLSI CMOS technology. It provides both in-phase and quadrature-phase differential outputs on a 60 MHz frequency range. The measured phase noise at 1 kHz offset from the carrier is about -92 dBc/Hz. The oscillator current consumption is 3 mA on a 3.3 V voltage supply.

A multiphase phase/frequency detector-based frequency synthesizer

The paper presents a multiphase phase/frequency detector for a PLL-based frequency synthesizer that shares the phase correction information N times in the period of an RF step. The multiphase PFD provides a better rejection of reference spurious tone and reduces the charge pump current without bandwidth and loop filter modification. The 800 MHz MPFD PLL has been implemented in a STMicroelectronics BiCMOS 2.5 V 0.25 /spl mu/m technology.

Impact of PLL 1/f 2 and white phase noise in RF bandpass sampling processing

This work presents a new method to numerically calculate the signal to jitter distortion ratio (SDjR) for any modulated input which is bandpass sampled in the presence of jitter. The numerical method matches the derived analytical equations. It is shown that the impact of white phase noise depends on the signal center frequency and the sub sampling factor while the impact of correlated jitter depends mostly on the signal center frequency. By separating the impact of both phase noise types on the SDjR, specifications for PLL phase noise are derived for a given sampling frequency.

Ultra low power bandpass sampling architectures using Lamb Wave filters

This article analyzes the use Lamb Wave Resonators (LWR) for IF filtering in RF Band pass Sampling (BPS) receivers. A filtering mask applicable to a bi-mode (Bluetooth Low Energy and IEEE 802.15.4) receiver is derived for the proposed BPS architecture and is used as design target for an IF filters based on LWR technology. A system-level design method is employed to analyze the impact of three different configurations for the analog IF filter: no filter, medium performance filter, and optimized filter. It is shown how block specifications can be relaxed thanks to the use of LWR filters.

Systematic design methodology for on-chip transformers with patterned ground shield

In this paper, we present a systematic design procedure for on-chip transformers with patterned ground shield fabricated in silicon IC technology. The design procedure is based on transformers key geometrical parameters, on process technology specifications, and on a wide-band and compact equivalent circuit model for on-chip transformers. The main aim is to provide designer with transformers with appropriate transformation ratio, optimum insertion loss at the targeted work frequency, and designated primary and secondary inductance values. Verification with measurement data from SiGe process demonstrates performance prediction and excellent scalability of the design methodology. This technique is suitable for design and optimization of Si-based RF integrated circuit applications

Phase error determination in GMSK modulated fractional-N PLL

Phase error contributors in a GMSK modulated fractional-N synthesizer are defined : the impulse response length and the oversampling ratio of the Gaussian filter, and the order and resolution of the /spl Sigma//spl utri/ converter. A method to optimise them is presented.