Olivier Mazouffre

Clock generator using factorial DLL for video applications

This paper presents a clock generator dedicated to front-end processors for LCD and plasma monitor video applications. The topology is based on a factorial DLL, which can support all kind of standards (from VGA up to SXGA). Fabricated in a 2.5 V, 0.25 /spl mu/m, 6-metal CMOS VLSI process from STMicroelectronics, the maximum r.m.s. measured jitter is 17 ps. The power consumption is 17 mW at 200 MHz output frequency. The low cost area (0.08 mm/sup 2/) and the fully integrated structure make it well suited for such a video market.

A Radiation-Hardened Injection Locked Oscillator Devoted to Radio-Frequency Applications

Implemented in a 0.25 mum SiGe technology, a 5.2 GHz Injection Locked Oscillator (ILO) for Radio-Frequency (RF) applications is shown to be intrinsically radiation-hardened. Design principles and laser-based testing results are presented

2-4 and 9-12 Gb/s CMOS fully integrated ILO-based CDR

A CDR dedicated to satellite data link is presented. The clock recovery function is made-up of an Injection Locked Oscillator combined with an analog phase alignment circuit. The circuit covers two bit-rate ranges: 2.2 to 4.3 Gb/s and 9.1 to 12.1 Gb/s. It was designed in 130 nm CMOS bulk process from STMicroelectronics. The overall power dissipation is 400 mW in the first bit-rate range and 480 mW in the second including 220 mW for I/O buffers. The eye opening at 10-9 of bit error rate is 940 mUI/440 mV at 3.1 Gb/s and 720 mUI/300 mV at 10.3 Gb/s.

A fully integrated 24 GHz fractional PLL with a low-power synchronized ring oscillator divider

This paper presents the design and the experimental measurements of a 24 GHz fully integrated fractional PLL with a new low power prescaler. This circuit is implemented in a 0.25 /spl mu/m SiGe:C process from STMicroelectronics (BiCMOS7RF). The PLL power dissipation is 148 mW and fulfills a 24.8 to 26.8 GHz frequency locking range, while exhibiting a phase noise of -97 dBc/Hz at 100 kHz from the carrier. The simulated PLL unity-gain bandwidth is 27 MHz, with a phase margin of 56 /spl deg/. The PLL uses a new latch-based prescaler (SRO) which exhibits a very low power dissipation of 0.74 GHz/mW.

A 2 GHz 2 mW SiGe BiCMOS frequency divider with new latch-based structure

A low power (2 mW) 2 GHz BiCMOS divider dedicated to UNITS is presented. The divider uses a new latch-based structure to obtain a division-by-4 with only two low-speed D-latches. The modulus can be 64 or 72 by the use of phase switching between the different quadrature outputs. The core of the programmable divider fabricated in 0.25 /spl mu/m STMicroelectronics SiGe BiCMOS technology occupies 0.025 mm/sup 2/ and consumes 1.3 mA at 1.5 V. The residual phase noise at the output is less than -100 dBc/Hz at an offset of 1 kHz from the carrier.

SiGe Clock and Data Recovery System Based on Injection-Locked Oscillator for 100 Gbit/s Serial Data Link

Clock and data recovery (CDR) systems are the first logic blocks in serial data receivers and the latters performance depends on the CDR. In this paper, a 100 Gbit/s CDR designed in 130 nm BiCMOS SiGe is presented. The CDR uses an injection locked oscillator (ILO) which delivers the 100 GHz clock. The inherent phase shift between the recovered clock and the incoming data is compensated by a feedback loop which performs phase and frequency tracking. Furthermore, a windowed phase comparator has been used, first to lower the classical number of gates, in order to prevent any delay skews between the different phase detector blocks, then to decrease the phase comparator operating frequency, and furthermore to extend the ability to track zero bit patterns The measurements results demonstrate a 100 GHz clock signal extracted from 50 Gb/s input data, with a phase noise as low as 98 dBc/Hz at 100 kHz offset from the carrier frequency. The rms jitter of the 25 GHz recovered data is only 1.2 ps. The power consumption is 1.4 W under 2.3 V power supply.

A Heavy-Ion Tolerant Clock and Data Recovery Circuit for Satellite Embedded High-Speed Data Links

A clock and data recovery (CDR) circuit dedicated to satellite embedded high-speed data links is implemented in a 0.13 mum CMOS technology. Its radiation hardening is obtained thanks to an innovative architecture based on an injection-locked oscillator (ILO) associated with a phase-alignment circuit. Its low single-event transient (SET) sensitivity is shown thanks to heavy-ion and laser testing.

VHDL-AMS model of an injection locked VCO

A VHDL-AMS model of an injection locked voltage controlled oscillator is presented in this paper. The model is valid for any harmonic of the synchronization signal. Properties such as locking-range, bandwidth and settling time are taken into account. The model is used in mixed simulations to reduce the computation time. A comparison with a schematic LC oscillator shows very good correlation.

A 675 /spl mu/W 5 GHz low-voltage BiCMOS synchronized ring oscillator based prescaler

This paper presents the design and the experimental measurements of a 5 GHz divide-by-4 prescaler for 802.11a and HiperLAN2 applications. The presented circuit is implemented in a 0.25μm BiCMOS SiGe process from STMicroelectronics. The prescaler is optimized for low power operation. It uses a Synchronized Ring Oscillator architecture based on two low-voltage differential bipolar latches with PMOS loads. The prescaler draws 520 μA from a 1.3 V power supply, its operating frequency is from 4.7 GHz to 6.8 GHz with a sensitivity of -10 dBm, and its efficiency is about 10 GHz/mW.

A low phase noise signal generation system for Ka-Band P2P applications based on an injection-locked frequency tripler

A signal generation system composed by a subharmonic VCO followed by an injection-locked frequency tripler (ILFT) is designed in a 0.25 μm BiCMOS SiGe:C technology. The ILFT implements a cascoded current-biased common emitter configuration that exploits the second harmonic of the VCO to enhance the efficiency in the generation of the injecting signal responsible for the ILFT locking. At 30.8GHz, the system achieves a phase noise of -112 dBc/Hz at 1 MHz offset. The total current consumption is 38 mA for a supply voltage of 2.5 V.