Oluwayomi Adamo

Joint scheme for physical layer error correction and security

We present a joint scheme that combines both error correction and security at the physical layer. In conventional communication systems, error correction is carried out at the physical layer while data security is performed at an upper layer. As a result, these steps are done as separate steps. However there has been a lot of interest in providing security at the physical layer. As a result, as opposed to the conventional system, we present a scheme that combines error correction and data security as one unit so that both encryption and encoding could be carried out at the physical layer. Hence, in this paper, we present an Error Correction-Based Cipher (ECBC) that combines error correction and encryption/decryption in a single step. Encrypting and encoding or decoding and decrypting in a single step will lead to a faster and more efficient implementation. One of the challenges of using previous joint schemes in a communications channel is that there is a tradeoff between data reliability and security. However, in ECBC, there is no tradeoff between reliability and security. Errors introduced at the transmitter for randomization are removed at the receiver. Hence ECBC can utilize its full capacity to correct channel errors.We show the result of randomization test on ECBC and its security against conventional attacks. We also present the nonpipelined and pipelined hardware architecture of ECBC, and the result of the FPGA implementation of the ECBC encryption.We also compare these results with non-ECBC schemes.

VLSI architecture and FPGA prototyping of a digital camera for image security and authentication

Two fundamental operations performed by a digital camera are image capturing and storing. The images are subsequently transmitted in various forms over appropriate media. These images are always vulnerable to various forms of copyright attacks and ownership issues. This paper introduces a digital camera with built-in copyright protection and security mechanism for images produced by it. Since the proposal of the trustworthy digital camera by Friedman [1], significant research has been done in developing algorithms for watermarking and encryption with the aim of using them in digital cameras. However, only few of these efforts are involved with the architectural development of the entire digital camera. Incorporation of encryption and watermarking together in the digital camera will assist in protecting and authenticating image files. In this paper, we present an architecture and a hardware efficient FPGA based watermark module towards the development of the complete digital camera.

VLSI Architecture of an Invisible Watermarking Unit for a Biometric-Based Security System in a Digital Camera

Due to the need for increased border security, we present a novel system in the form of a digital camera that embeds biometric data into an image. The embedding process is performed using an invisible watermarking algorithm that allows for verification of the image as well as the identity of the carrier. This paper presents an area efficient and high performance VLSI architecture implementing the invisible watermarking algorithm towards the development of the camera.

Smaller Split L-1 Data Caches for Multi-core Processing Systems

As more cores (processing elements) are included in a single chip, it is likely that the sizes of per core L-1 caches will become smaller while more cores will share L-2 cache resources. It becomes more critical to improve the use of L-1 caches and minimize sharing conflicts for L-2 caches. In our prior work we have shown that using smaller but separate L-1 array data and L-1 scalar data cache, instead of a larger single L-1 data cache, can lead to significant performance improvements. In this paper we will extend our experiments by varying cache design parameters including block size, associativity and number of sets for L-1 array and L-1 scalar caches. We will also present the affect of separate array and scalar caches on the non-uniform accesses to different (L-1) cache sets exhibited while using a single (L-1) data cache. For this purpose we use third and fourth central moments (skewness and kurtosis), which characterize the access patterns. Our experiments show that for several embedded benchmarks (from MiBench) split data caches significantly mitigate the problem of non-uniform accesses to cache sets (leading to more uniform utilization of cache resources, reduction of conflicts to cache sets, and minimizing hot spots in cache). They also show that neither higher set-associativities nor large block sizes are necessary with split cache organizations.

Physical Layer Error Correction Based Cipher

In conventional communication systems, error correction is carried out at the physical layer while data security is performed performed at an upper layer. As a result, these steps are done as separate steps. As opposed to this conventional system, we present a scheme that combines error correction and data security as one unit so that both encryption and encoding could be carried out at the physical layer. Hence, in this paper, we present an Error Correction Based Cipher (ECBC) that combines error correction and encryption/decryption in a single step. Encrypting and encoding or decoding and decrypting in a single step will lead to a faster and more efficient implementation. One of the challenges of using previous joint schemes in a communications channel is that there is a tradeoff between data reliability and security. However in ECBC, there is no trade off between reliability and security. Errors introduced at the transmitter for randomization are removed at the receiver. Hence ECBC can utilize its full capacity to correct channel errors. We show the result of randomization test on ECBC and its security against conventional attacks. We also present the result of the FPGA implementation of the ECBC encryption.

Hardware/software co-design approach for a DCT-based watermarking algorithm

The rapid increase in the distribution of digital multimedia data over networks creates the need for copyright protection. Watermarking is one of the techniques that can be used for this copyright protection. Many authors have proposed pure software or hardware solutions for the implementation of watermarking algorithms. In this paper we propose a hardware/software co-design approach for the implementation of the watermarking algorithm. Processes that demand high performance are implemented in hardware while those that are not computationally expensive are implemented in software. As a result, power consumption is reduced since only portion of the algorithm is implemented in hardware. In this paper we implement a DCT-based visible watermarking algorithm. Our system is implemented on a Xilinx Virtex-II Pro board. 21% of the slices were utilized with a maximum frequency of 131.092 MHz

Joint encryption error correction and modulation (JEEM) scheme

The major challenges facing resource constrained wireless devices are error resilience, security, and speed. In order to address these challenges, we present a physical layer encryption scheme that is capable of providing data reliability, secrecy and integrity. In addition, the scheme is also able to modulate the data. We construct joint encryption, error correction and modulation scheme to facilitate secure, reliable and efficient data transmission. This scheme is based on McEliece public key cryptosystem.

Hardware based encryption for wireless networks

We present an encryption scheme that is based on Error Correcting Codes (ECC). This scheme has the potential for reducing hardware usage due to hardware reuse. In this scheme, instead of having separate unit for encryption and error correction, the two schemes are carried out as a single step thereby using only one unit. The scheme exploits the characteristics of the ECC, and channel for achieving secrecy. The pipelined architecture and the result of its FPGA implementation is presented. We also show that the scheme is secure against conventional attacks and has also passed randomization test.