Saleh R. Al-Araji

Digital Phase Lock Loops

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Improved First-Order Time-Delay Tanlock Loop Architectures

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A time-delay digital tanlock loop

This paper presents a study of the performance of the first-order time-delay digital tanlock loop (TDTL). It proposes a number of modified loop architectures that overcome some of the original TDTL design limitations. Simulation results indicate that the new architectures, which include delay switching, gain adaptation and a combination of both techniques, improve the TDTL performance in terms of acquisition speed, locking range and resilience to frequency disturbances. The first-order TDTL was also implemented on a field programmable gate array (FPGA). The real-time results from the FPGA implementation are in agreement with the ones obtained through simulation

Performance evaluation of CIR based location fingerprinting

A digital tanlock loop (DTL) that utilises a constant time-delay unit instead of the constant 90/spl deg/ phase-shifter is proposed to reduce the complexity of implementation and rid the circuit of the practical problems, approximations and limitations caused by the 90/spl deg/ phase-shifter. The time-delay digital tanlock loop (TDTL) preserves the most important features of the conventional DTL (CDTL) and introduces improvement over the first-order CDTL under suitable choice of the circuit parameters.

Unified Analysis of Cooperative Spectrum Sensing Over Composite and Generalized Fading Channels

Location fingerprinting has received considerable attention as a practical solution to the indoor localization problem. Specifically Received Signal Strength (RSS) based fingerprinting has been studied extensively and some improvements in performance have been reported for certain pattern recognition algorithms. Recently channel impulse response (CIR) based fingerprinting received attention due to its potential for significant improvements in accuracy. The performance evaluation of CIR fingerprinting, however, has not been addressed adequately in literature. This paper presents the performance evaluation of CIR location fingerprinting in an indoor environment. A simulation framework has been developed using the Ray-Tracing software to emulate the indoor wireless channel. The CIR-based simulation results showed noticeable improvements in the location estimation compared to the RSS-based approach. The paper highlights new findings for some parameters that affect the performance of the CIR-based fingerprinting with respect to the system bandwidth and training point spacing.

Linearized Phase Detector Zero Crossing DPLL Performance Evaluation in Faded Mobile Channels

In this paper, we investigate the performance of cooperative spectrum sensing (CSS) with multiple-antenna nodes over generalized and composite fading channels. To this end, we approximate the probability density function (pdf) of the signal-to-noise ratio (SNR) of various fading channels using the mixture Gamma (MG) distribution. Based on this, we derive an exact closed-form expression and a generic infinite series representation for the corresponding probability of energy detection, along with a finite upper bound for the involved truncation error. Both expressions have a relatively simple algebraic form that gives them convenience in handling both analytically and numerically. Furthermore, the composite effect of multipath fading and shadowing scenarios in CSS is mitigated by applying an optimal fusion rule that minimizes the total error rate (TER), where the optimal number of nodes is derived under the Bayesian criterion, assuming erroneous feedback channels. We also extend the derived average detection probability to include diversity reception techniques, namely, maximal-ratio combining, square-law combining, and square-law selection (SLS). For the SLS, we demonstrate the existence of an error rate floor as the number of antennas of the cognitive radio nodes increases in erroneous decision feedback channels. Accordingly, we derive the optimal rule for the number of antennas that minimizes the TER in the SLS framework. Monte Carlo simulations are presented to corroborate the analytical results and to provide illustrative performance comparisons and insights between different composite fading channels.

Impulsive noise reduction techniques based on rate of occurrence estimation

Zero Crossing Digital Phase Locked Loop with Arc Sine block (AS-ZCDPLL) is used to linearize the phase difference detection, and enhance the loop performance. The loop has faster acquisition, less steady state phase error, and wider locking range compared to the conventional ZCDPLL. This work presents a Zero Crossing Digital Phase Locked Loop with Arc Sine block (ZCDPLL-AS). The performance of the loop is analyzed under mobile faded channel conditions. The mobile channel is assumed to be two path fading channel corrupted by additive white Gaussian noise (AWGM). It is shown that for a constant filter gain, the frequency spread has no effect on the steady state phase error variance when the loop is subjected to a phase step. For a frequency step and under the same conditions, the effect on phase error is minimal.

Adaptive zero-crossing digital phase-locked loop for packet synchronization

This paper presents a system with auto selection technique to reduce impulsive noise effect in wireless communication systems. The impulsive noise is detected through comparison with a fixed reference. The selection of the appropriate reduction technique to be applied is based on an estimation of the rate of impulsive noise occurrence. The proposed system uses subtraction-gating for low occurrence rate, conventional limiting for high occurrence rate, and passes the incoming signal to the output in the absence of impulsive noise. The results for QAM and FSK through simulation as well as real-time implementation on an FPGA development system are presented and show marked improvement in the bit error rate in each case.

Synchronization of a Single-phase Photovoltaic Generator With the Low-Voltage Utility Grid

This paper describes the design and performance analysis of a new approach for frequencysynchronization and transfer over packet networks. The proposed system utilizestimestamps-based with raised cosine pulse shaping first order adaptive zero-crossing digital phase-locked loop (AZC-DPLL). The system is designedto recover frequency as well as packets, independently of the input signal level in the presence of noise. This technique provides reliable locking by adjusting the loop gain, with the aid of finite state machine (FSM), and hence both system locking range and acquisition are improved.

Time delay digital tanlock loop with linearized phase detector

The increased generation of electrical energy from renewable sources and its integration into the low voltage grid have necessitated regulations governing the connection of renewable energy generators to the grid. This was deemed necessary to preserve the integrity and the correct operation of the grid. This paper presents a new architecture of a hybrid phase lock loop circuit topology for synchronizing a single-phase inverter fed from a renewable energy source such as a photovoltaic (PV) generator to the low voltage grid. The system uses a digital phase lock loop (DPLL) architecture, which is based on the arctan phase detector, driving a phase lock loop (PLL) to synchronize a PV inverter with the grid. The proposed system has been tested by simulation using simulink /matlab . The test results demonstrate the ability of the system to synchronize a PV inverter with the grid and to re-establish synchronization following a sudden perturbation in the grid voltage such as a single or a multistep change in phase. The system is digital and can be readily implemented using an FPGA (field programmable gate array) and hence can be easily embedded in a home or small scale single-phase PV inverter.