Omer Vikinski

Enhancing circuits and systems supply noise sensitivity characterization using on-package droop inducers

This paper presents design and implementation of noise inducer devices mounted on the package of a full featured microprocessor. Such assembly enables vast sensitivity characterization capabilities of the chip circuits and systems to supply noises. Prototype vehicle encompassing five separate 45nm CMOS process droop inducer devices stimulating four separate supply rails of a 32nm CMOS process microprocessor is reported. Multiple empirical results arising from the combined operation of the noise inducers and the microprocessor chip were obtained and analyzed.

CPU Power Delivery Impedance Profile Resonances Impact on Core FMAX

CPU core FMAX dependence on power delivery impedance profile resonances is investigated. Repetitive on/off stimulus degrades FMAX more than a step di/dt stimulus. Multiple resonances may have an additive effect on power supply voltage drops

Architecture constraints over dynamic current consumption

Microprocessor architecture poses constraints over the dynamic load consumption. Those constraints limit the range of hypothetical stimuli that the power delivery scheme can experience. Some guiding rules for power delivery quality relaxation can be deduced.

Controlled broadband load modules for generic noise injection at package and board level

Noise injection into power supply rails during chip validation can offer insight for effective power delivery design and to assist product certification. There are no available commercial solutions that offer broadband stimuli application for such aim. The paper suggests few implementations for such modules, emphasizing generic interfaces and the specific application pros and cons. Some prototyping attempts were made and both of their modeling and empirical results are included. The data indicate a strong contribution of the module interface parasitical properties to the resulting spectral range and distortion of the module loading stimuli versus the desired reference.

Embedded Power Delivery Decoupling in Small Form Factor Test Sockets

Growing gaps between testing and system environments is being observed for small form factor microprocessors. Power delivery high frequency resonances are significantly higher at test compared to actual system. Those gaps translate to poor yield for high performance products. Low inductance array capacitor implanted inside the test socket body is proposed. This feature can compensate for the power delivery gaps mentioned. Prototype for this advanced test socket was constructed. The paper will present simulated and measured data of the modified test socket performance and reliability.

CMOS ICs power-supply related decoupling properties

On-die decoupling plays important role in CMOS integrated circuits power delivery. A consistent extraction and modeling methodology of on-die inherent and intentional decoupling elements is presented. Measurements show accurate correlation to simulation of die capacitance.

Spectral relations of supply noise and jitter with regular and feed forward clocking schemes

High frequency supply noise affects chip performance in mechanisms that go beyond logic path failures due to voltage drops. One of the dominant chip performance degradation mechanisms due to high frequency noise is the direct introduction of clock jitter. Basic modeling studies powered by Fourier analysis help establish a clear and fundamental understanding of how noise is translated into jitter in the clock distribution path. In this context oscillator feed forward mechanism is also explored and analysis of its spectral response reveals how, once tuned properly, it benefits frequency boost.

Improved impedance profile prediction using non-linear switching regulator model

Switching voltage regulators determine the power rails impedance profile at the low frequency range. The regulator electrical model along with the rail passive network enables the prediction of the design impedance profile. The accuracy gained by using a non-linear regulator model is emphasized in the paper. The impedance profile resonances are under-estimated while using a linear average regulator model. The miss prediction is more severe as the amount of regulator filter capacitance is reduced. Accurate prediction of a marginal regulator design thus necessitates the usage of a switching regulator model.

The Second Generation Intel® Core™: A highly integrated high performance multi IA-core and processor graphics chip

This paper describes the Second Generation Intel® Core™ processor, a 32nm monolithic die integrating four IA cores, a processor graphics and a memory controller. The die was designed for high performance but without compromising the part power consumption or the part and system cost. To achieve these targets a modular design methodology was devised, this methodology allows fast configuration of the die to achieve the optimal performance/cost/power point for a specific market segment. In this paper some of the techniques used to control the die and package cost are described. Special attention is given to debug-ability hooks that considerably reduce the system time-to-market of this kind of highly integrated processors.

3D mobile CPU system assembly by Z-axis stack connector solutions

Module daughter cards are conventional approach in electronic integrated system solutions. Applying same principals for CPU products was abandoned some generations ago, yet may still hold some potential for concurrent and future products. Board to board stack connectors may allow growing the interface pin count versus conventional edge connectors. This alternative assembly scheme can offer competitive mechanical height and peripheral integrated chips performance versus the common PGA CPU sockets. Key area for performance boost may be the memory interface.