Gijung Ahn

An experimental high-density DRAM cell with a built-in gain stage

A new high-density DRAM cell concept is proposed and experimentally demonstrated. This cell, composed of two transistors and one capacitor, generates a large bit line signal with a small cell capacitance during the read cycle. Since it does not need a large storage capacitance and one transistor is stacked on the top of the other transistor, the cell size is small and can be easily scaled down for future generations of memory devices. The unit cell size fabricated using a 4 M SRAM process without any process modification is 1.8 /spl mu/m/spl times/2.85 /spl mu/m. The proposed cell can be adopted to store multi-bit information. The fabricated prototype cell shows a resolution of about 3.5 bit. >

A CMOS serial link for fully duplexed data communication

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 /spl mu/m CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns. >

A 5-Gb/s 0.25-/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A variable-interval oversampling clock/data recovery circuit (CDR) provides robust operation under varying jitter conditions. An eye-measuring loop in the CDR enables data recovery at maximum eye-opening, responding to the amount and shape of jitter. The CDR in 0.25 /spl mu/m CMOS shows <10/sup -13/ BER for 2/sup 7/-1 PRBS (pseudo-random-bit-sequence) at 5GBaud.

A low-jitter 5000ppm spread spectrum clock generator for multi-channel SATA transceiver in 0.18/spl mu/m CMOS

A low-jitter 5000ppm spread-spectrum clock generator is implemented in a 0.18/spl mu/m CMOS process. By using 10 multi-phase clocks and a /spl Delta//spl Sigma/ modulator with periodic input, the chip has a deterministic jitter of 25ps due to spread-spectrum clocking and an amount of spreading of 5000ppm.

A 0.6-2.5 GBaud CMOS tracked 3/spl times/ oversampling transceiver with dead-zone phase detection for robust clock/data recovery

Tracked 3/spl times/ oversampling with dead-zone phase detection is used in a receiver for robust clock/data recovery in the presence of excessive jitter and ISI. The transceiver, in 0.25 /spl mu/m CMOS, operates at 2.5 GBaud over 10 m 150 /spl Omega/ STP cable and at 1.25 GBaud over 25 m with <10/sup -13/ BER.

A Cmos Serial Link For 1 Gbaud Fully Duplexed Data Communication

This paper describes a CMOS serial link allowing fully duplexed 1 Gbaud serial data communication. The bidirectional serial link comprises a transmitter, a bidirectional bridge, an impedance matching circuit, a 4 GHz data oversampler, and a digital PLL. Fully duplexed serial data communication is realized by the bidirectional bridge and process- independent clock and data recovery is accomplished by the digital PLL. A single channel serial link and a charge pump PLL are integrated in a chip. The chip is fabricated using 1.2 pm CMOS process technology. INTRODUCTION Today, data rates become higher on various data communication fields. A high speed bidirectional serial link is a robust, low-cost solution to the high data rate requirements of chip-to-chip, board-to-board, and system- to-system communication. The bidirectional serial link can be applied to processor-to-processor communications, graphics super computers, and I-IDTV, which require the highest data rate, and also to various I/O channels, LANs, satellite, fiber data communications. This paper proposes a CMOS bidirectional serial link allowing fully duplexed data transfers at 1 Gbaud.

A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminator for high-speed NRZ data transmission

A large-swing, voltage-mode driver and an on-chip termination circuit are presented for high-speed nonreturn-to-zero (NRZ) data transmission through a copper cable. The proposed driver with active pull-up and pull-down can generate a 700-mV signal to deliver a 2 Gbaud serial NRZ data stream. Low output impedance offered by simple negative-feedback resistors alleviates the detrimental effect of the parasitic capacitance by supplying fast current impulses. A proposed on-chip termination circuit provides termination impedance to a mid-supply termination voltage with the benefit of reduced parasitic capacitance and better termination characteristics compared with off-chip termination. The driver and termination circuits have been incorporated in a 2 Gbaud transceiver chip and fabricated in 0.35 /spl mu/m CMOS technology. Measurements show a 1.4 V differential swing with a slew rate of 2.5 V/ns at the receiver output and a 65% reduction of reflection by the on-chip termination circuit with power consumption of 191 mW at 3.3 V supply.

A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link

A quad-channel 0.6-3.2 Gb/s/channnel transceiver using eight independent phase-locked loops (PLLs) shows a 1-ps rms random jitter performance without interchannel interference. The PLL employs a folded starved inverter with high supply/substrate noise immunity and an analog coarse-tuning scheme for both seamless frequency acquisition and N-fold voltage-controlled-oscillator (VCO) gain reduction. A fixed-interval charge pumping is adopted for wide pumping-current range and large jitter tolerance. A wide-range delayed-locked loop (DLL) is utilized as a clock and reset generator for an elastic buffer. The transceiver, implemented in a 0.18-/spl mu/m CMOS technology, operates across a 30-in FR-4 backplane up to 3.2 Gb/s/ch with a bit-error rate of less than 10/sup -13/.

A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control

A multi-rate transceiver incorporating TX slew control with >2times range, PLL with <0.5times loop-filter area using capacitance multiplication, and DeltaSigmaZ-SSCG having 11.7dB peak reduction is designed in 0.13mum CMOS. Occupying 2.33mm2 with TX operable up to 8.5Gb/s, the quad transceiver consumes 386mW from 1.2V supply and has a BER<10-14 at 6Gb/s over an 8m cable with 22dB loss

A 1.25-GBaud CMOS transceiver with on-chip terminator and voltage mode driver for Gigabit Ethernet 1000Base-X

This paper presents a 1.25-GBaud transceiver chip implemented with 0.35-/spl mu/m CMOS technology, which can be used as an IEEE 802.32 Gigabit Ethernet 1000Base-X physical layer. A voltage mode driver and an on-chip termination circuit reduce signal distortion in the pseudo-ECL serial data stream in the presence of parasitic capacitance and inductance as well as reducing the number of external components. A differential voltage swing of output driver is 1400 mV and power consumption is 510 mW at 3.3 V supply under normal operation.