Won-Chul Song

A 10-b 20-Msample/s low-power CMOS ADC

A single-ended input but internally differential 10 b, 20 Msample/s pipelined analog-to-digital converter (ADC) is demonstrated with 4 mW per stage using a single 5 V supply. The prototype ADC made of an input sample and hold (S/H) plus 8 identical unscaled pipelined stages consumes 50 mW including power consumed by a bias generator and two internal buffer amplifiers driving common-mode bias lines. Key circuits developed for this low-power ADC are a dynamic comparator with a capacitive reference voltage divider that consumes no static power, a source-follower buffered op amp that achieves wide bandwidth using large input devices, and a self-biased cascode biasing circuit that tracks power supply variation. The ADC implemented using a double-poly 1.2 /spl mu/m CMOS technology exhibits a DNL of /spl plusmn/0.65 LSB and a SNDR of 54 dB while sampling at 20 MHz. The chip die area is 13 mm/sup 2/. >

A 1 GHz image-rejection down-converter in 0.8 /spl mu/m CMOS technology

A 1 GHz image-rejection down-converter implemented in a 0.8 /spl mu/m CMOS process is presented. The down-converter consists of a quadrature generator and mixers. The proposed architecture has an image-rejection characteristic that are insensitive to the phase error of the higher frequency first local oscillator (LO). The down-converter has an image-rejection characteristic of 29.3 dB under 2/spl deg/ phase error of the lower frequency second LO. The down-converter dissipates 108 mW at a 3.3 V supply.

A 622 Mb/s CMOS clock recovery PLL with time-interleaved phase detector array

A 622 Mb/s clock recovery PLL for SDH/SONET OC-12 is implemented in a 0.8 /spl mu/m CMOS technology. With time-interleaved phase detection scheme, this PLL performs clock recovery and 1:8 demultiplexing simultaneously. It dissipates 200 mW with a single 5 V supply, whose core occupies 800/spl times/900 /spl mu/m/sup 2/. RMS jitter of the recovered 78 MHz clock is 46 ps (0.36%).

A 200 MHz/90 dB gain range CMOS VGA

A novel CMOS Variable Gain Amplifier (VGA) with high frequency and high dynamic range is proposed. It has a controllable gain range from -45 dB to +45 dB by external control voltage as well as enhanced operating frequency up to 200 MHz. It is fabricated in 0.35 /spl mu/m CMOS technology with the core area of 580 /spl mu/m/spl times/660 /spl mu/m. It consumes only 10.8 mA at 3.3 V supply voltage.

A CMOS Implementation Of CDMA/FM IF Signal Processor

A CDMAiFM IF IC is implemented using 0.8 pm 2-metal 2-poly CMOS process. This IC integrates both CDMA and FM IF signal processing functions required for dual mode cellular phone. Rx and Tx frequencies are 85.38 MHz and 130.38 MHz, respectively. The chip size is 5.5 x 6.3 mm2 and the maximum power consumption is 230 mW.

A 3.3 V 0.8 /spl mu/m CMOS single chip IF IC for CDMA/FM cellular phone

A 3.3 v 150 mW IF IC is implemented using 0.8 /spl mu/m CMOS process. This IC integrates both CDMA and FM IF signal processing units and interfaces between IF signals and baseband modem. Rx mixer down-converts 85.38 MHz IF signals into baseband signal, and Tx mixer based on a replica transconductor up-converts baseband signal into a 130.38 MHz IF signal. The chip size is 5.5/spl times/6.3 mm/sup 2/.