Óscar Jiménez

A Versatile Power Electronics Test-Bench Architecture Applied to Domestic Induction Heating

The design of new power-converter solutions optimized for specific applications requires, at a certain step, the design and implementation of several prototypes in order to verify the converter operation. This is a time-consuming task which also involves a significant economical cost. The aim of this paper is to present a versatile power electronics architecture which provides a tool to make the implementation and evaluation of new power converters straightforward. The adopted platform includes a versatile control architecture and a modular power electronics hardware solution. The control architecture is a field-programmable-gate-array-based system-on-programmable-chip solution which combines the advantages of the processor-firmware versatility and the effectiveness of ad hoc paralleled digital hardware. Moreover, the modular power electronics hardware provides a fast method to reconfigure the power-converter topology. The architecture proposed in this paper has been applied to the development of power converters for domestic induction heating, although it can be extended to other applications with similar requirements. A complete development test bench has been carried out, and some experimental results are shown in order to verify the proper system operation.

High-Level Synthesis for Accelerating the FPGA Implementation of Computationally Demanding Control Algorithms for Power Converters

Recent advances in power electronic converters highly rely on the development of new control algorithms. These implementations often require complex control architectures featuring microprocessors, digital signal processors, and field-programmable gate arrays (FPGAs). Whereas software implementations are feasible for most power electronics practitioners, FPGA implementations with ad-hoc digital hardware are often a challenging design task. This paper deals with the design and development of control systems for power converters using high-level synthesis tools. In particular, the Xilinx Vivado HLS tool is evaluated for the design of a computationally demanding application, the real-time load estimation for resonant power converters using parametric identification methods. The proposed methodology allows the designer to use a high-level description language, e.g., C, to describe the identification algorithm functionality, and the tool automatically generates the hardware floating-point data-path and the control unit. Besides, it allows a fast design-space exploration through synthesis directives, and pipelining and parallelization are automatically performed to meet timing constraints. The evaluation performed in the study-case control architecture shows a significant design complexity reduction. As a consequence, high-level synthesis tools should be considered as a new paradigm in accelerating digital design for power conversion systems.

Real-Time FPGA-Based Hardware-in-the-Loop Simulation Test Bench Applied to Multiple-Output Power Converters

This paper presents a hardware-in-the-loop (HIL) simulation technique applied to a series-resonant multiple-output inverter for new multi-inductor domestic induction heating platforms. The control of the topology is based on a system-on-programmable chip (SoPC) solution, which combines the MicroBlaze embedded soft-core processor and a customized peripheral that generates the power converter control signals. The firmware is written in C, and the customized peripheral is described using a hardware description language. Simulating the whole system using digital or mixed-signal simulation tools is a very time-consuming task due to the embedded processor model complexity, and additionally, it does not support tracing C instructions. To overcome these limitations, this paper proposes a real-time simulation test bench. The embedded processor core, peripherals, and the power converter model are all implemented into the same field-programmable gate array (FPGA). Using the hardware and software debugging tools supplied by the FPGA vendor, currents and voltages of the power converter model are monitored, and firmware C instructions are traced while running on the embedded processor core. Then, it is presented a design flow that is proven to be an effective and low-cost solution to verify the functionality of the customized peripheral and to implement a platform to perform firmware verification.

Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-Width Modulators

Advantages of digital control in power electronics have led to an increasing use of digital pulse-width modulators (DPWM). However, the clock frequency requirements may exceed the operational limits when the power converter switching frequency is increased, while using classical DPWM architectures. In this paper, we present two synchronous designs to increase the resolution of the DPWM implemented on field programmable gate arrays (FPGA). The proposed circuits are based on the on-chip digital clock manager block present in the low-cost Spartan-3 FPGA series and on the I/O delay element (IODELAYE1) available in the high-end Virtex-6 FPGA series. These solutions have been implemented, tested, and compared to verify the performance of these architectures.

An FPGA-Based Gain-Scheduled Controller for Resonant Converters Applied to Induction Cooktops

Domestic induction heating appliances have become popular due to their advantages such as efficiency, fast heating, cleanliness, and safety. In order to achieve high efficiency, induction cooktops usually features resonant converters in which the inductor-vessel system is a part of the resonant tank. Thus, the inductor-vessel system impedance sets the point of operation of the power converter. Due to the variability of the load with multiple parameters such as temperature, geometry, and material, the resonant converter has to work with highly varying operating conditions. When designing a classical controller, the controller gain is selected to assure the system stability in the whole range of operation and for a large amount of vessels. This study proposes an FPGA-based gain scheduled controller which makes use of the information of the modulation parameters and an online impedance identification system. As a result, the proposed controller significantly improves the converter dynamic response, improving the performance and safety operation of the power converter. The proposed control algorithm has been experimentally verified using a domestic induction heating prototype, proving the feasibility of this proposal.

FPGA-Based Test-Bench for Resonant Inverter Load Characterization

Resonant converters often require accurate load characterization in order to ensure appropriate and safe control. Besides, for systems with a highly variable load, as the induction heating systems, a real-time load estimation is mandatory. This paper presents the development of an FPGA-based test-bench aimed to extract the electrical equivalent of the induction heating loads. The proposed test-bench comprises a resonant power converter, sigma-delta ADCs, and an embedded system implemented in an FPGA. The characterization algorithm is based on the discrete-time Fourier series computed directly from the ΔΣ ADC bit-streams, and the FPGA implementation has been partitioned into hardware and software platforms to optimize the performance and resources utilization. Analytical and simulation results are verified through experimental measurements with the proposed test-bench. As a result, the proposed platform can be used as a load identification tool either for stand-alone or PC-hosted operation.

Analysis and Implementation of FPGA-Based Online Parametric Identification Algorithms for Resonant Power Converters

Resonant power converters are widely used due to their advantages in terms of size, efficiency, and power density. One of the main design difficulties derives from the need to accurately tune the resonant tank and the operating conditions to achieve the desired performance. This is especially challenging in those applications in which either the resonant tank or the operating conditions are highly variable. This paper proposes and compares several implementations of online parametric identification algorithms to identify the resonant tank of power converters taking advantage of field-programmable gate array technology. The proposed implementations are based on the phase-sensitive detector algorithm, which ensures an accurate harmonic identification of the resonant load. The proposed identification system is tested using a resonant power converter prototype applied to induction heating systems, proving the feasibility and accuracy of this proposal.

Implementation of an FPGA-Based Online Hardware-in-the-Loop Emulator Using High-Level Synthesis Tools for Resonant Power Converters Applied to Induction Heating Appliances

This paper proposes a field-programmable-gate-array-based emulator of the series-resonant half-bridge inverter for measuring the inverter efficiency and detecting hard-switching conditions. The proposed emulator is able to compute the converter operating conditions and efficiency each mains half-cycle, providing useful information for the control unit. In addition, it is designed taking advantage of recent advances in high-level synthesis tools, which provides an optimized and straightforward implementation. The proposed emulator has been applied to an induction heating (IH) appliance as an example of efficient and environmentally friendly appliances with a major economic and social impact. The obtained results are compared with classical offline simulation and experimental measurements, proving that the proposed emulator achieves the required accuracy for the IH application. As a consequence, the proposed system can be used for improving the system safety and optimizing the converter efficiency and reliability.

Real-time FPGA-based Hardware-in-the-Loop development test-bench for multiple output power converters

The implementation of multiple-inductor power converters requires often the development of specific purpose control architectures to obtain the most of the converter. These are usually based on a processor, which provides software flexibility, and specific purpose hardware, which provides customized functionalities. In addition, recent trends suggest the integration of both functionalities in a single chip using an embedded processor and customized hardware, providing a System-on-Programmable-Chip (SoPC) solution. The aim of this paper is to implement a SoPC system which provides flexibility and customized hardware, and develop a real-time FPGA-based development test-bench based on the Hardware-In-the-Loop (HIL) simulation technique, which accelerates simulation, reduces design cycle times, and allows software and power converter modulation schemes development. The complete system is integrated by a multiple-inductor power converter and an FPGA, which contains a MicroBlaze embedded processor and a specific purpose Digital Pulse Width Modulator (DPWM). HIL at power level is applied by implementing the power converter model into the FPGA. It has been designed with the VHDL-2008 float_pkg package, which allows a straight-forward implementation. As a result, the digital and the analog power converter signals can be traced by means of ChipScope tool, and the processor software can be traced by means of a software debugger tool.

Design and Evaluation of a Low-Cost High-Performance

The advantages of resonant power converters, such as high efficiency and high power density, make them a suitable solution for domestic applications such as induction heating (IH) cookers. The control systems of these appliances require performing accurate and smooth power control while assuring the safety of the power devices. In order to accomplish these tasks, it is necessary to have information about the target output power, which is selected by the user, and the specific parameters of the output current. In this paper, a single-bit second-order sigma-delta ( Σ-Δ) analog-to-digital converter (ADC) is proposed to measure the magnitude of interest in resonant power converters. An optimized digital low-pass filter architecture is proposed to extract the output current from the digitized bit stream. This filter improves the accuracy while having low logic-resource consumption. The proposed ADC has been verified using a resonant inverter applied to the IH cooktop application. The inverter switching frequency is in the range of 40-80 kHz. A statistical analysis of the final measurement system has been performed to assess the system accuracy. The proposed system achieves good accuracy in the inverter operating range.