J.I. Artigas

Location-based services for elderly and disabled people

Many techniques have been developed to perform indoor location. Each strategy has its own advantages and drawbacks, with the application demanding location information the main determinant of the system to be used. In this paper, a system is presented that serves location to innovative services for elderly and disabled people, ranging from alarm and monitoring to support for navigation and leisure. The system uses ZigBee and ultrasound to fulfill the application requirements, differing in this respect from all other existing systems. ZUPS (ZigBee and ultrasound positioning system) provides wide multicell coverage, easy extension, robustness even in crowded scenarios, different levels of precision depending on the users profile and service requirements (from a few centimeters to meters), limited infrastructure requirements, simple calibration, and cost-effectiveness. The system has been evaluated from the technical, functional, and usability standpoints, with satisfactory results, and its suitability has also been demonstrated in a residence for people with disabilities located in Zaragoza, Spain.

FPGA-Based Power Measuring for Induction Heating Appliances Using Sigma–Delta A/D Conversion

This paper presents a field-programmable gate array (FPGA) implementation of a digital circuit that measures in real time the output power of medium-frequency (25-50 kHz) induction-heated cooking appliances. The voltage and current are sensed using first-order sigma-delta (SigmaDelta) analog-to-digital converters. The power-measuring algorithm is very simple while maintaining good accuracy. The algorithm is developed using a hardware description language (VHDL). The digital circuit, the power converter, the signal conditioning circuits, and the SigmaDelta modulators are simulated all together using a mixed-signal (analog + digital) simulation tool. The algorithm error is obtained in simulation computing the average power using VHDL-Analog and Mixed-Signal Extension Language (VHDL-AMS), and the influence of different parameters is analyzed. Finally, the digital circuit is implemented in the FPGA, and the simulations are experimentally verified.

Efficiency optimization in ZVS series resonant inverters with asymmetrical voltage-cancellation control

This paper presents a time-domain analysis and a computerized search algorithm for optimizing the efficiency in zero-voltage switching (ZVS) full-bridge series resonant inverters with asymmetrical voltage-cancellation (AVC) control for different load quality factors. The optimum AVC control found allows all the switches to be turned on with zero voltage with the minimum switching frequency. In order to minimize losses, the switching frequency is kept as close as possible to resonance. The optimum AVC control is compared with previous fixed or narrow frequency range control strategies to show that it improves performance over all the output power range for different loads. The detailed steady-state analysis carried out here increases the precision of the first-harmonic analysis of a previous work, which is especially important with distorted output currents due to low load quality factors or highly asymmetrical modulation strategies. The theoretical results are verified experimentally.

Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-Width Modulators

Advantages of digital control in power electronics have led to an increasing use of digital pulse-width modulators (DPWM). However, the clock frequency requirements may exceed the operational limits when the power converter switching frequency is increased, while using classical DPWM architectures. In this paper, we present two synchronous designs to increase the resolution of the DPWM implemented on field programmable gate arrays (FPGA). The proposed circuits are based on the on-chip digital clock manager block present in the low-cost Spartan-3 FPGA series and on the I/O delay element (IODELAYE1) available in the high-end Virtex-6 FPGA series. These solutions have been implemented, tested, and compared to verify the performance of these architectures.

FPGA-Based Test-Bench for Resonant Inverter Load Characterization

Resonant converters often require accurate load characterization in order to ensure appropriate and safe control. Besides, for systems with a highly variable load, as the induction heating systems, a real-time load estimation is mandatory. This paper presents the development of an FPGA-based test-bench aimed to extract the electrical equivalent of the induction heating loads. The proposed test-bench comprises a resonant power converter, sigma-delta ADCs, and an embedded system implemented in an FPGA. The characterization algorithm is based on the discrete-time Fourier series computed directly from the ΔΣ ADC bit-streams, and the FPGA implementation has been partitioned into hardware and software platforms to optimize the performance and resources utilization. Analytical and simulation results are verified through experimental measurements with the proposed test-bench. As a result, the proposed platform can be used as a load identification tool either for stand-alone or PC-hosted operation.

Power Measurement by Output-Current Integration in Series Resonant Inverters

In many applications, efficiency and service quality are improved with an appropriate power control. This paper focuses on a power-measurement method designed to deal with medium/high frequencies (tens to hundreds of kilohertz). It requires a previous knowledge of application and exploits some characteristics of the power topology and control, in this case, a full-bridge series resonant inverter. It is a new method based on a low-cost analog circuit that integrates the high-frequency load current, in order to reduce the computational complexity of measuring power. Harmonic analysis is carried out to determine the A/D converter requirements, and the theoretical results are verified using a digital-signal-processor (DSP)-based experimental setup. The power measurement may be implemented on the microcontroller or low-performance DSP used to control the power stage, with an error below of 2% independent of the load and mains variations.

Modeling of resonant inverters with high harmonic content using the extended describing function method

This paper analyzes the extended describing function technique (EDF) for modeling a resonant power converter applied to induction heating applications. Since in this specific application operating conditions may be far from resonance, this paper is focused on extending the model to several harmonics and verifying its validity range. The main goal is to obtain accurate control-to-power transfer functions which predict the resonant inverter small-signal behaviour. A simulation test bench is proposed and evaluated for measuring the open-loop duty cycle and frequency-to-power transfer function plots from time domain simulations of the switching model. Finally, the accuracy of the model is analyzed.

Comparing simulation alternatives of FPGA-based controllers for switching converters

Digital controllers implemented in an FPGA for switching power converters are becoming an important alternative to the traditional analog solutions. Assuming that the digital controller is described using a hardware description language, this work gives an overview of models, and mixed-signal simulation alternatives that support the simulation as a whole of the digital controller with the power electronic circuit, in order to validate the closed-loop behavior.

An electromagnetic-based model for calculating the efficiency in domestic induction heating appliances

An electromagnetic-based model for calculating the efficiency of litz-wire planar inductors for domestic induction heating appliances is developed. This efficiency will be determined by the relationship between the losses in the windings and the power delivered by eddy currents in the vessel. Therefore, it will depend on the geometry and properties of the vessel as well as winding parameters. Considering both dependences simultaneously, an analytical model of the induction efficiency is developed and experimentally verified in this paper. The model includes the dependences of the excitation current frequency and the properties of the load and windings. In this study the model is used to design the optimum number of strands of the litz wire used for windings, and to test the induction efficiency of different loads.

VLSI architecture for lossless compression of medical images using the discrete wavelet transform

This paper presents a VLSI architecture to implement the forward and inverse 2-D discrete wavelet transform (FDWT/IDWT), to compress medical images for storage and retrieval. Lossless compression is usually required in the medical image field. The word length required for lossless compression makes too expensive the area cost of the architectures that appear in the literature. Thus, there is a clear need for designing an architecture to implement the lossless compression of medical images using DWT. The datapath word-length has been selected to ensure the lossless accuracy criteria leading a high speed implementation with small chip area. The result is a pipelined architecture that supports single chip implementation in VLSI technology. The architecture has been simulated in VHDL and has a hardware utilization efficiency greater than 99%. It can compute the FDWT/IDWT at a rate of 3.5 512/spl times/512 12 bit images/s corresponding to a clock speed of 33 MHz.