I. Urriza

Real-Time FPGA-Based Hardware-in-the-Loop Simulation Test Bench Applied to Multiple-Output Power Converters

This paper presents a hardware-in-the-loop (HIL) simulation technique applied to a series-resonant multiple-output inverter for new multi-inductor domestic induction heating platforms. The control of the topology is based on a system-on-programmable chip (SoPC) solution, which combines the MicroBlaze embedded soft-core processor and a customized peripheral that generates the power converter control signals. The firmware is written in C, and the customized peripheral is described using a hardware description language. Simulating the whole system using digital or mixed-signal simulation tools is a very time-consuming task due to the embedded processor model complexity, and additionally, it does not support tracing C instructions. To overcome these limitations, this paper proposes a real-time simulation test bench. The embedded processor core, peripherals, and the power converter model are all implemented into the same field-programmable gate array (FPGA). Using the hardware and software debugging tools supplied by the FPGA vendor, currents and voltages of the power converter model are monitored, and firmware C instructions are traced while running on the embedded processor core. Then, it is presented a design flow that is proven to be an effective and low-cost solution to verify the functionality of the customized peripheral and to implement a platform to perform firmware verification.

Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-Width Modulators

Advantages of digital control in power electronics have led to an increasing use of digital pulse-width modulators (DPWM). However, the clock frequency requirements may exceed the operational limits when the power converter switching frequency is increased, while using classical DPWM architectures. In this paper, we present two synchronous designs to increase the resolution of the DPWM implemented on field programmable gate arrays (FPGA). The proposed circuits are based on the on-chip digital clock manager block present in the low-cost Spartan-3 FPGA series and on the I/O delay element (IODELAYE1) available in the high-end Virtex-6 FPGA series. These solutions have been implemented, tested, and compared to verify the performance of these architectures.

An FPGA-Based Gain-Scheduled Controller for Resonant Converters Applied to Induction Cooktops

Domestic induction heating appliances have become popular due to their advantages such as efficiency, fast heating, cleanliness, and safety. In order to achieve high efficiency, induction cooktops usually features resonant converters in which the inductor-vessel system is a part of the resonant tank. Thus, the inductor-vessel system impedance sets the point of operation of the power converter. Due to the variability of the load with multiple parameters such as temperature, geometry, and material, the resonant converter has to work with highly varying operating conditions. When designing a classical controller, the controller gain is selected to assure the system stability in the whole range of operation and for a large amount of vessels. This study proposes an FPGA-based gain scheduled controller which makes use of the information of the modulation parameters and an online impedance identification system. As a result, the proposed controller significantly improves the converter dynamic response, improving the performance and safety operation of the power converter. The proposed control algorithm has been experimentally verified using a domestic induction heating prototype, proving the feasibility of this proposal.

Real-time FPGA-based Hardware-in-the-Loop development test-bench for multiple output power converters

The implementation of multiple-inductor power converters requires often the development of specific purpose control architectures to obtain the most of the converter. These are usually based on a processor, which provides software flexibility, and specific purpose hardware, which provides customized functionalities. In addition, recent trends suggest the integration of both functionalities in a single chip using an embedded processor and customized hardware, providing a System-on-Programmable-Chip (SoPC) solution. The aim of this paper is to implement a SoPC system which provides flexibility and customized hardware, and develop a real-time FPGA-based development test-bench based on the Hardware-In-the-Loop (HIL) simulation technique, which accelerates simulation, reduces design cycle times, and allows software and power converter modulation schemes development. The complete system is integrated by a multiple-inductor power converter and an FPGA, which contains a MicroBlaze embedded processor and a specific purpose Digital Pulse Width Modulator (DPWM). HIL at power level is applied by implementing the power converter model into the FPGA. It has been designed with the VHDL-2008 float_pkg package, which allows a straight-forward implementation. As a result, the digital and the analog power converter signals can be traced by means of ChipScope tool, and the processor software can be traced by means of a software debugger tool.

Comparing simulation alternatives of FPGA-based controllers for switching converters

Digital controllers implemented in an FPGA for switching power converters are becoming an important alternative to the traditional analog solutions. Assuming that the digital controller is described using a hardware description language, this work gives an overview of models, and mixed-signal simulation alternatives that support the simulation as a whole of the digital controller with the power electronic circuit, in order to validate the closed-loop behavior.

VLSI architecture for lossless compression of medical images using the discrete wavelet transform

This paper presents a VLSI architecture to implement the forward and inverse 2-D discrete wavelet transform (FDWT/IDWT), to compress medical images for storage and retrieval. Lossless compression is usually required in the medical image field. The word length required for lossless compression makes too expensive the area cost of the architectures that appear in the literature. Thus, there is a clear need for designing an architecture to implement the lossless compression of medical images using DWT. The datapath word-length has been selected to ensure the lossless accuracy criteria leading a high speed implementation with small chip area. The result is a pipelined architecture that supports single chip implementation in VLSI technology. The architecture has been simulated in VHDL and has a hardware utilization efficiency greater than 99%. It can compute the FDWT/IDWT at a rate of 3.5 512/spl times/512 12 bit images/s corresponding to a clock speed of 33 MHz.

Power Measurement for Resonant Power Converters Applied to Induction Heating Applications

Nowadays, induction heating (IH) technology is dominating the domestic cooking market due to its advantages such as safety, cleanness, and high efficiency. Such high efficiency and high power density implementations are achieved by means of resonant power converters and, consequently, these need to be accurately controlled. This paper proposes a field-programmable gate array-based online power measurement system which allows the control system to perform the proper power control. The proposed power measurement system measures the output power from the digitized output voltage and current through two low-cost 1-bit second-order ΣΔ analog-to-digital converters. The bitstreams have been analyzed and, taking into account the results, several measurement approaches have been proposed and analyzed. Then, a noise sensitivity analysis has been performed in order to verify the proposed measurements methods. The analytical and simulation results have been tested through a resonant power converter applied to domestic IH whose switching frequency varies from 30 to 80 kHz. A statistical analysis of the implemented measurement approaches has been carried out in order to evaluate the system accuracy. Finally, the selected measurement method has been verified for several vessels. As a conclusion, an accurate and cost-effective output power measurement system is obtained, which can be applied to any resonant converter in the frequency operation range.

Choice of word length in the design of a specialized hardware for lossless wavelet compression of medical images

Image compression plays an important role in the archiving and transmission of medical images. Discrete cosine transform (DCT)- based compression methods are not suitable for medical images because of block-like image artifacts that could mask or be mistaken for pathology. Wavelet transforms (WTs) are used to overcome this problem. When implementing WTs in hardware, finite precision arithmetic introduces quantization errors. However, lossless compression is usually required in the medical image field. Thus, the hardware designer must look for the optimum register length that, while ensuring the lossless accuracy criteria, will also lead to a high-speed implementation with small chip area. In addition, wavelet choice is a critical issue that affects image quality as well as system design. We analyze the filters best suited to image compression that appear in the literature. For them, we obtain the maximum quantization errors produced in the calculation of the WT components. Thus, we deduce the minimum word length required for the reconstructed image to be numerically identical to the original image. The theoretical results are compared with experimental results obtained from algorithm simulations on random test images. These results enable us to compare the hardware implementation cost of the different filter banks. Moreover, to reduce the word length, we have analyzed the case of increasing the integer part of the numbers while maintaining constant the word length when the scale increases.

FPGA-based high resolution synchronous digital pulse width modulator

Advantages of digital control in power electronics have led to an increasing use of digital pulse width modulators (DPWM). However, the clock frequency requirements may exceed reasonable limits when the power converter switching frequency is increased while using classical DPWM architectures. This paper presents a novel synchronous design to increase the resolution of DPWM implemented on Field Programmable Gate Arrays (FPGA). The proposed circuit utilizes the Phase Shift (PS) functional unit of the on-chip Digital Clock Manager (DCM) blocks available on modern FPGAs, operating in fixed mode. This solution has been implemented, tested and compared to other implementations.

Using Mixed-Signal Simulation to Design a Digital Power Measurement System for Induction Heating Home Appliances

Mixed-simulation tools arise as efficient tools in the design flow of power converter controllers. Nowadays power converters are controlled by digital circuits modeled using hardware description languages. These models are validated by simulation and mixed signal simulators provide a way to simulate the system as a whole. In this work we present the use of these tools in the design and validation of a power measurement system.