Owen Sullivan

Array of Thermoelectric Coolers for On-Chip Thermal Management

Site-specific on-demand cooling of hot spots in microprocessors can reduce peak temperature and achieve a more uniform thermal profile on chip, thereby improve chip performance and increase the processor’s life time. An array of thermoelectric coolers (TECs) integrated inside an electronic package has the potential to provide such efficient cooling of hot spots on chip. This paper analyzes the potential of using multiple TECs for hot spot cooling to obtain favorable thermal profile on chip in an energy efficient way. Our computational analysis of an electronic package with multiple TECs shows a strong conductive coupling among active TECs during steady-state operation. Transient operation of TECs is capable of driving cold-side temperatures below steady-state values. Our analysis on TEC arrays using current pulses shows that the effect of TEC coupling on transient cooling is weak. Various pulse profiles have been studied to illustrate the effect of shape of current pulse on the operation of TECs considering crucial parameters such as total energy consumed in TECs peak temperature on the chip, temperature overshoot at the hot spot and settling time during pulsed cooling of hot spots. The square root pulse profile is found to be the most effective with maximum cooling and at half the energy expenditure in comparison to a constant current pulse. We analyze the operation of multiple TECs for cooling spatiotemporally varying hot spots. The analysis shows that the transient cooling using high amplitude current pulses is beneficial for short term infrequent hot spots, but high amplitude current pulse cannot be used for very frequent or long lasting hot spots.

Hotspot Cooling in Stacked Chips Using Thermoelectric Coolers

3-D technologies with stacked chips have the potential to provide new chip architecture, and improved device density, performance, efficiency, and bandwidth. The increased power density in 3-D technologies can become a daunting challenge for heat removal. Furthermore, power density can be highly nonuniform, leading to time- and space-varying hotspots, which can severely affect performance and reliability of integrated circuits. It is important to mitigate on-chip thermal gradients while considering the associated cooling costs. One efficient method of hotspot thermal management is to use superlattice thermoelectric coolers (TECs), which can provide on demand and localized cooling. In this paper, a detailed 3-D thermal model of a stacked electronic package with two dies and four ultrathin integrated TECs is developed to investigate the efficacy of TECs in hotspot cooling for 3-D technology. A strong vertical coupling has been observed between TECs located in top and bottom dies. Bottom TECs can significantly heat the top hotspots in both steady-state and transient operation. TECs need to be carefully placed inside the package to avoid such undesired heating. Thermal contact resistances between dies, inside the TEC module, and between TEC and heat spreader are shown to have a crucial effect on the TEC performance. We observe up to 5.6

Prospects of active cooling with integrated super-lattice based thin-film thermoelectric devices for mitigating hotspot challenges in microprocessors

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Thermoelectric Coolers for Thermal Gradient Management on Chip

of active hotspot cooling in steady state and 7.4

Control Principles and On-Chip Circuits for Active Cooling Using Integrated Superlattice-Based Thin-Film Thermoelectric Devices

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On-Chip Power Generation Using Ultrathin Thermoelectric Generators

of active hotspot cooling using a square root current pulse.

Thermoelectric Coolers for Hotspot Thermal Management of 3D Stacked Chips

Super-lattice thin-film thermoelectric coolers (TEC) are emerging as a promising technology for hot spot mitigation in microprocessors. This paper studies the prospect of on-demand cooling with advanced TECs integrated at the back of the heat spreader inside a package (integrated TEC). The thermal compact models of the chip and package with integrated TECs are developed and used for steady-state and transient temperature analysis. The control principles for TEC assisted transient cooling are presented and their impact on reducing thermal violations in microprocessors and TEC energy dissipations are discussed.

Compact Model of Thermoelectric Coolers on a Micro-Electronic Chip

Site-specific and on-demand cooling of hot spots in the microprocessors can provide efficient cooling solution, improve its performance and increase its life time by reducing peak temperature and achieving more uniform thermal profile on the chip. Thermoelectric coolers (TEC) have the potential to provide such efficient cooling of hot spots on a chip. We investigate pulse cooling behavior of ultra-thin multiple TEC devices integrated inside the electronic package on the active side of a chip below the heat spreader. Various pulse profiles have been studied to obtain optimal shape of the current pulse in order to efficiently operate TECs considering crucial parameters such as the total energy consumed in TECs, peak temperature on the chip, temperature overshoot at hot spot and settling time during pulsed cooling of hot spots. The square root pulse profile is found to be most effective with maximum cooling and half the energy expenditure in comparison to a constant current pulse. It has been observed that high thermal contact resistances can entirely negate the transient cooling effect of the TECs. We analyze the operation of multiple TECs for cooling spatiotemporally varying hot spots. The analysis shows that the temperature of the hot spots can be retained below a threshold using transient current pulses through the TECs. This underlines the benefits of using multiple TECs for hot spot cooling in order to obtain favorable thermal profile on the chip in an energy efficient way.Copyright

Thermoelectric Generators Embedded in Microelectronic Chip

Superlattice thin-film thermoelectric coolers (TECs) are emerging as a promising technology for hot spot mitigation in microprocessors. This paper studies the prospect of on-demand cooling with advanced TECs integrated at the back of the heat spreader inside a package (integrated TEC). Using thermal compact models of the chip and package with integrated TECs, the control principles for TEC-assisted transient cooling are presented. The control principles are implemented in a 130-nm CMOS process and cosimulated with the thermal system to show their feasibility and energy overheads. The simulation results show potential for extending the time for which a chip and package can sustain a high power load.

3D Compact Model of Packaged Thermoelectric Coolers

Thermoelectric generators (TEGs) can significantly improve the net power consumption and battery life of the low power mobile devices or high performance devices by generating power from their waste heat. Recent advancements also show that the ultrathin thermoelectric devices can be fabricated and integrated within a micro-electronic package. This work investigates the power generation by an ultrathin TEG embedded within a micro-electronic package considering several key parameters such as load resistance, chip heat flux, and proximity of the TEG to chip. The analysis shows that the power generation from TEGs increases with increasing background heat flux on chip or when TEGs are moved closer to the chip. An array of embedded TEGs is considered in order to analyze the influence of multiple TEGs on total power generation and conversion efficiency. Increasing the number of TEGs from one to nine increases the useful power generation from 72.9 mW to 378.4 mW but decreases the average conversion efficiency from 0.47% to 0.32%. The average power generated per TEG gradually decrease from 72.9 mW to 42.0 mW when number of TEGs is increased from one to nine, but the total useful power generated using nine TEGs is significant and emphasize the benefits of using embedded TEGs to reduce net power consumption in electronics packages. [DOI: 10.1115/1.4027995]