Man Prakash Gupta

Ultrathin Thermoelectric Devices for On-Chip Peltier Cooling

The efficient usage of thermoelectric (TE) devices for microelectronics cooling application requires investigation and remedy of various obstacles such as integration of these devices with electronic package, parasitic contact resistances, and utilization of appropriate current pulses. We develop a computational model to investigate the effect of steady state and transient mode of operation of ultrathin thermoelectric cooler (TEC) devices on hot-spot cooling considering the effect of crucial thermal and electrical contact resistances. Our analysis shows that the transient pulses can be very effective in reducing the hot-spot temperature by 6-7°C in addition to the cooling achieved by the steady state current through the TEC device. We correlate the important characteristics of the transient temperature behavior of hot-spot under the TEC operation such as the maximum temperature drop (ΔTmax), time taken to achieve ΔTmax and temperature overshoot after turning off pulse current with the electrical and thermal contact resistances and Seebeck coefficient of the TE material. It has been observed that thermal and electrical contact resistances play a very crucial role in the performance of TEC devices as high values of these resistances can significantly diminish the effect of Peltier cooling during steady state operation. The effect of these parasitic resistances is even higher for the transient cooling of hot-spots by the pulsed current through the TEC device. High Seebeck coefficient of TE materials is desirable as it increases the figure of merit of TE devices. However, cooling capabilities of heat sink may become bottleneck to realize the benefits of very high Seebeck coefficient as the back heat flow from the hot side to cold side of TEC device diminishes the degree of cooling achieved by these ultrathin TECs.

Array of Thermoelectric Coolers for On-Chip Thermal Management

Site-specific on-demand cooling of hot spots in microprocessors can reduce peak temperature and achieve a more uniform thermal profile on chip, thereby improve chip performance and increase the processor’s life time. An array of thermoelectric coolers (TECs) integrated inside an electronic package has the potential to provide such efficient cooling of hot spots on chip. This paper analyzes the potential of using multiple TECs for hot spot cooling to obtain favorable thermal profile on chip in an energy efficient way. Our computational analysis of an electronic package with multiple TECs shows a strong conductive coupling among active TECs during steady-state operation. Transient operation of TECs is capable of driving cold-side temperatures below steady-state values. Our analysis on TEC arrays using current pulses shows that the effect of TEC coupling on transient cooling is weak. Various pulse profiles have been studied to illustrate the effect of shape of current pulse on the operation of TECs considering crucial parameters such as total energy consumed in TECs peak temperature on the chip, temperature overshoot at the hot spot and settling time during pulsed cooling of hot spots. The square root pulse profile is found to be the most effective with maximum cooling and at half the energy expenditure in comparison to a constant current pulse. We analyze the operation of multiple TECs for cooling spatiotemporally varying hot spots. The analysis shows that the transient cooling using high amplitude current pulses is beneficial for short term infrequent hot spots, but high amplitude current pulse cannot be used for very frequent or long lasting hot spots.

Impact of thermal boundary conductances on power dissipation and electrical breakdown of carbon nanotube network transistors

estimate the average CNT-SiO2 TBC as g � 0.16Wm � 1 K � 1 and the TBC at CNT junctions as GC � 2.4 pWK � 1 . We find the peak power dissipation in CN-TFTs is more strongly correlated to the TBC of the CNT-substrate interface than to the TBC at CNT junctions. Molecular dynamics simulations of crossed CNT junctions also reveal that the top CNT is buckled over � 30nm lengths, losing direct contact with the substrate and creating highly localized hot-spots. Our results provide new insights into CNT network properties which can be engineered to enhance performance of CN-TFTs for macro and flexible electronics applications. V C 2012 American

Proactive power migration to reduce maximum value and spatiotemporal non-uniformity of on-chip temperature distribution in homogeneous many-core processors

This paper presents a proactive spatiotemporal power multiplexing method to manage the thermal field in many-core processors. We first analyze the thermal field in many core processors in deep nanometer (to 16nm nodes). We show that the thermal field in many-core can have significant spatiotemporal non-uniformity along with high maximum temperature. For better reliability and improved cooling efficiency, it is important to achieve a lower peak temperature and a more uniform thermal field under all workload or utilization conditions. We propose proactive power migration to reduce spatial and temporal temperature difference, by redistributing the heat generating locations. The effectiveness of the proposed method is demonstrated for a 256 core many-core processor in predictive 16nm nodes.

On-chip Peltier cooling using current pulse

Thermoelectric coolers (TECs) can address an efficient removal of localized heat for a wide range of applications such as microelectronic processors, DNA micro arrays, lasers. The efficient usage of thermoelectric devices for these applications require investigation and remedy of various obstacles such as integration of these devices with electronic package, parasitic contact resistances and utilization of appropriate current pulses and control algorithms. We investigate the effect of steady state and transient mode of operation of ultrathin TEC devices on hot spot temperature reduction on a chip through a developed computational model. The numerical model incorporates the effect of thermal and electrical contact resistances to analyze the hot spot cooling. Our analysis shows that transient pulses can be very effective to reduce the hotspot temperature in addition to the cooling achieved by the steady state current through the device. Thermal and electrical contact resistance play a very crucial role in the performance of TEC devices as high values of these resistances can completely diminish the effect of Peltier cooling. The effect of these parasitic resistances is even higher for the transient cooling of hot-spots by the pulsed current through the device compared to the steady state operation.

High field breakdown characteristics of carbon nanotube thin film transistors

The high field properties of carbon nanotube (CNT) network thin film transistors (CN-TFTs) are important for their practical operation, and for understanding their reliability. Using a combination of experimental and computational techniques we show how the channel geometry (length L(C) and width W(C)) and network morphology (average CNT length L(t) and alignment angle distribution θ) affect heat dissipation and high field breakdown in such devices. The results suggest that when WC ≥ L(t), the breakdown voltage remains independent of W(C) but varies linearly with L(C). The breakdown power varies almost linearly with both W(C) and L(C) when WC >> L(t). We also find that the breakdown power is more susceptible to the variability in the network morphology compared to the breakdown voltage. The analysis offers new insight into the tunable heat dissipation and thermal reliability of CN-TFTs, which can be significantly improved through optimization of the network morphology and device geometry.

Thermoelectric Coolers for Thermal Gradient Management on Chip

Site-specific and on-demand cooling of hot spots in the microprocessors can provide efficient cooling solution, improve its performance and increase its life time by reducing peak temperature and achieving more uniform thermal profile on the chip. Thermoelectric coolers (TEC) have the potential to provide such efficient cooling of hot spots on a chip. We investigate pulse cooling behavior of ultra-thin multiple TEC devices integrated inside the electronic package on the active side of a chip below the heat spreader. Various pulse profiles have been studied to obtain optimal shape of the current pulse in order to efficiently operate TECs considering crucial parameters such as the total energy consumed in TECs, peak temperature on the chip, temperature overshoot at hot spot and settling time during pulsed cooling of hot spots. The square root pulse profile is found to be most effective with maximum cooling and half the energy expenditure in comparison to a constant current pulse. It has been observed that high thermal contact resistances can entirely negate the transient cooling effect of the TECs. We analyze the operation of multiple TECs for cooling spatiotemporally varying hot spots. The analysis shows that the temperature of the hot spots can be retained below a threshold using transient current pulses through the TECs. This underlines the benefits of using multiple TECs for hot spot cooling in order to obtain favorable thermal profile on the chip in an energy efficient way.Copyright

Thermal Investigation Into Power Multiplexing for Homogeneous Many-Core Processors

In this paper, a proactive thermal management technique called “power multiplexing” is explored for many-core processors. Power multiplexing involves redistribution of the locations of active cores at regular time intervals to obtain uniform thermal profile with low peak temperature. Three different migration policies namely random, cyclic, and global coolest replace have been employed for power multiplexing and their efficacy in reducing the peak temperature and thermal gradient on chip is investigated. For a given migration frequency, global coolest replace policy is found to be the most effective among the three policies considered as this policy provides 10 °C reduction in peak temperature and 20 °C reduction in maximum spatial temperature difference on a 256 core chip. Power configuration on the chip is characterized by a parameter called “proximity index” which emerges as an important parameter to represent the spatial power distribution on a chip. We also notice that the overall performance of the chip could be improved by 10% using global multiplexing.

Thermal mangament of multicore processors using power multiplexing

One of the novel methods for the thermal management of multi-core processors is power multiplexing (also known as core hopping) which involves dynamical change of the locations of active cores within the chip at fixed time intervals. The power multiplexing technique helps in reducing the number of hotspots on the chip by providing a spatially uniform thermal profile which in turn lowers the maximum temperature rise on the chip. We quantify the effects of power multiplexing on the thermal profile of multi-core processor chip. Different core migration policies have been implemented in an attempt to evolve an optimally suitable policy for the multiplexing purpose. We observe that the selection of appropriate migration policy and the migration rate can efficiently reduce the spatial non-uniformity and peak temperature on the chip. The ratio of active to total cores has been varied to accommodate and analyze the effect of varying computing workload. We correlated the cooling power with the peak temperature on the chip and discussed the efficient usage of core-migration policies in the context of the power reduction.

On-Chip Power Generation Using Ultrathin Thermoelectric Generators

Thermoelectric generators (TEGs) can significantly improve the net power consumption and battery life of the low power mobile devices or high performance devices by generating power from their waste heat. Recent advancements also show that the ultrathin thermoelectric devices can be fabricated and integrated within a micro-electronic package. This work investigates the power generation by an ultrathin TEG embedded within a micro-electronic package considering several key parameters such as load resistance, chip heat flux, and proximity of the TEG to chip. The analysis shows that the power generation from TEGs increases with increasing background heat flux on chip or when TEGs are moved closer to the chip. An array of embedded TEGs is considered in order to analyze the influence of multiple TEGs on total power generation and conversion efficiency. Increasing the number of TEGs from one to nine increases the useful power generation from 72.9 mW to 378.4 mW but decreases the average conversion efficiency from 0.47% to 0.32%. The average power generated per TEG gradually decrease from 72.9 mW to 42.0 mW when number of TEGs is increased from one to nine, but the total useful power generated using nine TEGs is significant and emphasize the benefits of using embedded TEGs to reduce net power consumption in electronics packages. [DOI: 10.1115/1.4027995]