P. A. Coxon

Performance of thin-film transistors on polysilicon films grown by low-pressure chemical vapor deposition at various pressures

Defect properties of undoped low-pressure chemical-vapor-deposited (LPCVD) polysilicon films have been investigated by capacitance techniques on a simple metal-oxide-semiconductor (MOS) capacitor structure. The results show that the effective density of bulk and interface trap states is almost independent of the deposition pressure. After reducing the polysilicon film thickness by etching, although the grain size decreases due to the columnar mode of growth at low pressures, the trap states density reduces significantly. This finding could be explained by the hypothesis that, during the growth of the material, impurities are segregated at the film surface by fast diffusion through the grain boundaries. The transport properties of 0.5- mu m-thick polysilicon films deposited at a pressure ranging from 100 to 0.5 mtorr were evaluated from measurements on thin-film transistors (TFTs). The results demonstrate that at high pressures the grain boundaries and at low pressures the polysilicon-SiO/sub 2/ interface roughness scattering are the main factors in determining the transistor performance. >

Effect of pressure on the growth of crystallites of low-pressure chemical-vapor-deposited polycrystalline silicon films and the effective electron mobility under high normal field in thin-film transistors

The morphology of polycrystalline films grown by low‐pressure chemical‐vapor deposition (LPCVD) is investigated by transmission electron microscopy (TEM) as a function of the film thickness, the deposition pressure, and the level of contamination. An orientation filtering mechanism, due to the growth‐velocity competition in the early stage of growth, is responsible for the preferred orientation of the films. The size of the crystallites, the surface roughness, and the type of the structural defects are investigated by combined cross‐sectional and plane‐view TEM analysis. In polycrystalline silicon thin‐film transistors (TFTs), the influence of surface roughness scattering on the mobility is investigated by measuring the effective electron mobility under high effective normal field at 295 and 77 K. Although the surface curvature is increased when the deposition pressure is decreased, the surface roughness scattering is constant in the deposition pressure range from 40 to 0.5 mTorr. By decreasing the deposi...

High‐performance thin‐film transistors from optimized polycrystalline silicon films

The performance of thin‐film transistors fabricated in unrecrystallized (small‐grain) polcrystalline silicon is shown to be greatly improved by depositing the films at much lower pressures than normally used in the low‐pressure chemical vapor deposition process. Electronic measurements on completed devices are presented and related to the film structure by transmission electron microscopy examination.

Effects of temperature and electrical stress on the performance of thin‐film transistors fabricated from undoped low‐pressure chemical vapor deposited polycrystalline silicon

The stability of thin‐film transistors (TFTs) fabricated from undoped low‐pressure chemical vapor deposited polycrystalline silicon under stress conditions (dc voltage and temperature) is investigated. It is demonstrated that the Si‐SiO2 interface morphology is critical for the TFT device performance. Device degradation and threshold voltage instabilities are mainly attributed to the roughened Si‐SiO2 interface.

Field‐effect conductance activation energy in an undoped polycrystalline silicon thin‐film transistor

We investigate the temperature dependence of the field‐effect (FE) conductance of thin‐film transistors on undoped polycrystalline silicon layers. The FE conductance is thermally activated at a fixed gate voltage. The conductance prefactor G0 increases exponentially with the FE activation energy Ea, in accordance with the Meyer–Neldel rule. Using these results, a model of exponentially decaying band tails explains the FE activation energy data. By fitting the FE activation energy data with the theory, we determine the trap distribution in polysilicon layers deposited at various pressures. The results indicate that the existence of band tails is not an intrinsic property of grain boundaries.

Crystallization of amorphous silicon by reconstructive transformation utilizing gold

A gold layer one order of magnitude thinner than the thickness of an amorphous silicon layer in intimate contact leads to the dissolution of the amorphous silicon into the liquid and the subsequent precipitation of crystalline Si as the liquid phase propagates into the amorphous phase at above eutectic temperatures. The crystalline Si precipitate has grain sizes of the order of 6 μm. The Si/Au liquid is very sensitive to constitutional supercooling and subsequent crystallization.

Leakage current of undoped LPCVD polycrystalline silicon thin-film transistors

The leakage current of thin-film transistors on undoped polycrystalline silicon layers, deposited by low-pressure chemical vapor deposition, is investigated in relation to the deposition pressure. For films deposited at pressure 40 mTorr, the leakage current I/sub L/ is controlled by the intrinsic resistivity of the film. The increase of the current I/sub L/ with increasing gate and drain bias voltages is due to the Joule-induced-heating effect. For films deposited at pressures below 40 mTorr, the leakage current is controlled by the reverse-biased junction at the drain end. In this case, the minimum leakage current is modeled as thermal generation current arising from midgap Coulombic defect trap states. When the gate and drain bias voltages are increased, the thermally generated current is enhanced by the Poole-Frenkel effect due to high electric fields at the drain junction. Such high electric fields at the drain end can arise from doping inhomogeneities because of fast diffusion through the grain boundaries of the implanted drain dopant. At high bias voltages, a deviation from linearity of the Poole-Frenkel current-voltage characteristics is observed due to the hot carrier effect. >

Control of the performance of polysilicon thin-film transistor by high-gate-voltage stress

The performance of low-pressure chemical-vapor-deposited (LPCVD) polycrystalline-silicon thin-film transistors (TFTs) can be controlled by applying a high-gate-voltage stress. The potential barrier height at the grain boundary is reduced after positive high-gate-voltage stress and then increases after negative high gate voltage stress. The experimental results indicate that Ca and Al ions or hydrogen atoms existing in the gate oxide may be able to passivate grain boundaries at the polysilicon-SiO/sub 2/ interface.<<ETX>>

Hopping conduction in undoped low‐pressure chemically vapor deposited polycrystalline silicon films in relation to the film deposition conditions

The conductivity of undoped low‐pressure chemically vapor deposited polycrystalline silicon films has been investigated in the temperature range 77–300 K as a function of the deposition conditions of the film. At low temperatures hopping conductivity has been identified. Decrease of the deposition pressure of the polysilicon film shifts the hopping region to lower temperatures and reduces the density of localized trap states and, also, the degree of disorder.

Influence of deposition pressure on the output characteristics of low pressure chemical vapor deposited polycrystalline silicon thin‐film transistors

The influence of the deposition pressure on the output characteristics of low pressure chemical vapor deposited polycrystalline silicon thin‐film transistors is investigated. The polysilicon films are deposited at pressures 40, 10, and 0.5 mTorr. For channel lengths L greater than 10 μm, the device has the conventional output characteristics dominated by the grain boundaries. In short‐channel devices (L<10 μm), the experimental results show the presence of the ‘‘kink’’ effect and a reduction of the threshold voltage at high drain biases. When the deposition pressure of the polysilicon layer decreases, despite the increase of the grain size, the kink effect becomes more pronounced due to the enhanced diffusion of dopants from the source and drain contacts along the grain boundaries. The enhanced dopant diffusion reduces the effective channel length resulting in higher channel electric fields and increased kink effect.