P. Baine

Ultralow silicon substrate noise crosstalk using metal Faraday cages in an SOI technology

Ultralow substrate crosstalk is demonstrated using a novel metal Faraday cage isolation scheme in silicon-on-insulator technology. Over ten times reduction in crosstalk is demonstrated up to 10 GHz, compared to previously reported substrate crosstalk suppression technologies.

Silicon-on-insulator substrates with buried tungsten silicide layer

Abstract Tungsten silicide layers can be incorporated into silicon-on-insulator (SOI) substrates produced by direct wafer bonding. The series resistance of collectors/drains in bipolar or smart-power circuits can be reduced to 2 Ω/sq. The out-diffusion of the buried implanted collector contact during the post-bond anneal can be eliminated by using rapid diffusivity of donors and acceptors in tungsten silicide subsequent to bond anneal. Optimisation of this process can provide better matching of vertical complementary bipolar transistors. A novel silicon-on-silicide-on-insulator structure is proposed for integrating p–i–n diodes with low loss coplanar wave-guide lines. This incorporates a polysilicon surface layer on the high resistivity handle wafer and a tungsten silicide back contact to the diode. CPW lines with microwave losses of 2 dB/cm have been obtained at 30 GHz. The incorporation of a tungsten silicide layer below the buried silicon dioxide layer can be used as a ground plane. A tungsten silicide ground plane used with a standard SOI test structures was found to increase the suppression of cross-talk by 20 dB in the frequency range 1–10 GHz. Other potential applications such as ground plane and double-gate MOSFETs are discussed.

Fermi level de-pinning of aluminium contacts to n-type germanium using thin atomic layer deposited layers

Fermi-level pinning of aluminium on n-type germanium (n-Ge) was reduced by insertion of a thin interfacial dielectric by atomic layer deposition. The barrier height for aluminium contacts on n-Ge was reduced from 0.7 eV to a value of 0.28 eV for a thin Al2O3 interfacial layer (∼2.8 nm). For diodes with an Al2O3 interfacial layer, the contact resistance started to increase for layer thicknesses above 2.8 nm. For diodes with a HfO2 interfacial layer, the barrier height was also reduced but the contact resistance increased dramatically for layer thicknesses above 1.5 nm.

Investigation of germanium implanted with hydrogen for layer transfer applications

The technology for thin Ge layer transfer by hydrogen ion-cut process is characterised in this work. Experiments were carried out to determine suitable hydrogen ion implantation doses in germanium for the low temperature ion cut process by examining the formation of blisters on implanted samples. Raman and Spreading Resistance Profiling (SRP) have been used to analyse defects in germanium caused by hydrogen implants. Bevelling has been used to facilitate probing beyond the laser penetration depth. Results of Raman mapping along the projection area reveal that after post implant annealing at 400 °C, some crystal damage remains, while at 600 °C, the crystal damage has been repaired. SRP shows that some amount of hydrogen acceptor states (~1Î1016 acceptors/cm2) remain after 600 °C. These are thought to be vacancy-related point defect clusters.

Electrical characterization of SOI substrates incorporating WSi/sub x/ ground planes

Silicon-on-insulator (SOI) substrates incorporating tungsten silicide ground planes (GPs) have been shown to offer the lowest reported crosstalk figure of merit for application in mixed signal integrated circuits. The inclusion of the silicide layer in the structure may lead to stress or defects in the overlying SOI layers and resultant degradation of device performance. It is therefore essential to establish the quality of the silicon on the GPSOI substrate. MOS capacitor structures have been employed in this paper to characterize these GPSOI substrates for the first time. High quality MOS capacitor characteristics have been achieved with minority carrier lifetime of /spl sim/0.8 ms. These results show that the substrate is suitable for device manufacture with no degradation in the silicon due to stress or metallic contamination resulting from the inclusion of the underlying silicide layer.

Silicon-on-insulator substrates with buried ground, planes (GPSOI)

Experimental s/sub 21/ transmission crosstalk studies have been conducted on silicon-on-insulator substrates with buried ground planes (GPSOIs) where a 2 /spl Omega/ per square metal-silicide buried ground plane existed between a 15 /spl Omega/-cm p-type silicon substrate and a 1 μm thick buried CVD oxide layer. Locally grounded transmission test structures fabricated on GPSOI were found to exhibit 20 dB increased crosstalk suppression compared to published data for high resistivity (200 /spl Omega/-cm) SOI substrates incorporating capacitive guard rings over a frequency range from 500 MHz to 50 GHz. This represents an order of magnitude improvement in crosstalk power suppression capability compared to existing state-of-the-art suppression techniques in silicon substrates.

Impact of buried oxide thickness and ground plane resistivity on substrate cross-talk in ground plane silicon-on-insulator (GPSOI) cross-talk suppression technology

The impact of changing the buried oxide thickness and the ground plane resistivity on the substrate cross-talk in ground plane silicon-on-insulator (GPSOI) cross-talk suppression technology is investigated. It is found that crosstalk increases with increasing oxide thickness for low resistivity ground planes but decreases with increasing oxide thickness for higher ground plane resistivities over certain frequency ranges. An optimum buried oxide thickness is identified.

Circular geometry transistors fabricated on germanium-on-alumina bonded substrates

Germanium(Ge) has attractive properties such as high carrier mobility, compatibility with high-K dielectrics, and lattice matched for GaAs growth. Germanium on insulator (GOI) (1) offers the advantages of germanium and combines them with those of silicon on insulator (SOI). Bonding to substrates which are thermally matched to Ge eases process temperature constraints and can have additional benefits depending on the substrate used. Transistors have previously been reported on a germanium on sapphire wafer bonded platform (2). Fine grain alumina offers a cheaper alternative to sapphire while still retaining advantages such as low substrate losses and better crosstalk suppression. In this work Circular Geometry MOS transistors fabricated and tested on germanium bonded to a fine grain alumina substrate (superstrate 997) are presented. The Ge on Alumina substrate was realised by bonding a polysilicon coated and subsequently planarised alumina substrate to a Umicore 2.7-2.9 ohmcm n-Ge substrate(3). After subsequent bond strength annealing at 150 C the Ge was thinned by precision in-house grinding and diamond particulate polishing leaving a thick 100μm Ge on Alumina layer. The ground and polished substrate is shown in figure 1. Circular geometry transistors were fabricated using a low temperature self aligned W gate fabrication process. The maximum temperature seen by the transistors was 450 C. The transistors having a W/L of 9 also employed a 20nm APCVD silicon dioxide layer as the gate dielectric. As a direct comparison identical transistors where fabricated on bulk Ge substrates with the same resistivity as the bonded structure. Figure 2 shows the resultant output characteristics obtained from both the bulk Ge device (2(a)) and the Ge on Alumina device (2(b)). As can be seen the bulk Ge showed better transistor characteristics exhibiting an effective mobility of 480 cm/Vs compared to 150cm/Vs. The Ge on Alumina substrate also shows significant series resistance. The decline in device performance was thought to be due to the poor surface roughness of the Ge on Al layer after polishing. It was found that by the addition of NaOCL into the polish process an improvement in the surface roughness of germanium was achieved from 2.5nm to 0.8nm.. Subsequently transistors fabricated on the improved reworked Ge layer produced improved characteristics comparable to those obtained in bulk Ge. Characteristics shown in figure 3 exhibit an effective mobility of 414 cm/Vs Low temperature investigation of the transistor operation on the Ge on Al devices was carried out over a range of temperatures from room temperature to 173 K on transistors having a W/L of 9. A MDC model 441 cryogenic probe station in combination with Agilent B1500 parameter analyser was employed for low temperature measurement. Device characteristics were seen to improve with an increase in effective mobility (μeff) and decrease in Sub threshold slope (S) observed with decreasing temperature. The improvement in transistor effective mobility is shown in figure 4. Table 1 offers a summary of the change in device characteristics with decreasing temperature.

Long-Range Lateral Dopant Diffusion in Tungsten Silicide Layers

Novel diode test structures have been manufactured to characterize long-range dopant diffusion in tungsten silicide layers. A tungsten silicide to p-type silicon contact has been characterized as a Schottky barrier rectifying contact with a silicide work function of 4.8 eV. Long-range diffusion of boron for an anneal at 900degC for 30 min has been shown to alter this contact to become ohmic. Long-range diffusion of phosphorus with a similar anneal alters the contact to become a bipolar n-p diode. Bipolar diode action is demonstrated experimentally for anneal schedules of 30 min at 900deg C, indicating long-range diffusion of phosphorus ( ~ 38 mum). SIMS analysis shows dopant redistribution is adversely affected by segregation to the silicide/oxide interface. The concept of conduit diffusion has been demonstrated experimentally for application in advanced bipolar transistor technology.

Conduit diffusion of dopants in tungsten silicide layers

Novel test diode structures have been manufactured to characterise dopant diffusion in tungsten silicide layers. Bipolar diode action is demonstrated experimentally for anneal schedules of 30 minutes at 900degC, indicating long- range diffusion of phosphorus (~ 38 mum). The work function of the silicide was found to be 4.8 eV. SIMS analysis shows dopant redistribution is effected by the segregation to the silicide/oxide interface. The concept of conduit diffusion has been demonstrated experimentally for application in advanced bipolar transistor technology.