M. Bain

Ultralow silicon substrate noise crosstalk using metal Faraday cages in an SOI technology

Ultralow substrate crosstalk is demonstrated using a novel metal Faraday cage isolation scheme in silicon-on-insulator technology. Over ten times reduction in crosstalk is demonstrated up to 10 GHz, compared to previously reported substrate crosstalk suppression technologies.

SiGe HBTs on bonded SOI incorporating buried silicide layers

A technology is described for fabricating SiGe heterojunction bipolar transistors (HBTs) on wafer-bonded silicon-on-insulator (SOI) substrates that incorporate buried tungsten silicide layers for collector resistance reduction or buried groundplanes for crosstalk suppression. The physical structure of the devices is characterized using cross section transmission electron microscopy, and the electrical properties of the buried tungsten silicide layer are characterized using sheet resistance measurements as a function of bond temperature. Possible contamination issues associated with the buried tungsten silicide layer are investigated by measuring the collector/base reverse diode tics. A resistivity of 50 /spl mu//spl Omega/cm is obtained for the buried silicide layer for a bond anneal of 120 min at 1000/spl deg/C. Collector/base reverse diode tics show a voltage dependence of approximately V/sup 1/2/, indicating that the leakage current is due to Shockley-Read-Hall generation in the depletion region. Fitting of the current-voltage tics gives a generation lifetime of 90 ns, which is as expected for the collector doping of 7 /spl times/ 10/sup 17/ cm/sup -3/. These results indicate that the buried tungsten silicide layer does not have a serious impact on junction leakage.

Silicon-on-insulator substrates with buried tungsten silicide layer

Abstract Tungsten silicide layers can be incorporated into silicon-on-insulator (SOI) substrates produced by direct wafer bonding. The series resistance of collectors/drains in bipolar or smart-power circuits can be reduced to 2 Ω/sq. The out-diffusion of the buried implanted collector contact during the post-bond anneal can be eliminated by using rapid diffusivity of donors and acceptors in tungsten silicide subsequent to bond anneal. Optimisation of this process can provide better matching of vertical complementary bipolar transistors. A novel silicon-on-silicide-on-insulator structure is proposed for integrating p–i–n diodes with low loss coplanar wave-guide lines. This incorporates a polysilicon surface layer on the high resistivity handle wafer and a tungsten silicide back contact to the diode. CPW lines with microwave losses of 2 dB/cm have been obtained at 30 GHz. The incorporation of a tungsten silicide layer below the buried silicon dioxide layer can be used as a ground plane. A tungsten silicide ground plane used with a standard SOI test structures was found to increase the suppression of cross-talk by 20 dB in the frequency range 1–10 GHz. Other potential applications such as ground plane and double-gate MOSFETs are discussed.

Electrical characterization of SOI substrates incorporating WSi/sub x/ ground planes

Silicon-on-insulator (SOI) substrates incorporating tungsten silicide ground planes (GPs) have been shown to offer the lowest reported crosstalk figure of merit for application in mixed signal integrated circuits. The inclusion of the silicide layer in the structure may lead to stress or defects in the overlying SOI layers and resultant degradation of device performance. It is therefore essential to establish the quality of the silicon on the GPSOI substrate. MOS capacitor structures have been employed in this paper to characterize these GPSOI substrates for the first time. High quality MOS capacitor characteristics have been achieved with minority carrier lifetime of /spl sim/0.8 ms. These results show that the substrate is suitable for device manufacture with no degradation in the silicon due to stress or metallic contamination resulting from the inclusion of the underlying silicide layer.

Characterization of CVD tungsten deposited by silane reduction

The deposition of tungsten by silane reduction of WF6 was investigated to determine the effect of the deposition chemistry on the layer properties. The influence of the deposition chemistry on the titanium adhesion layer was also investigated. To perform a direct comparison of the effect of the deposition parameters on the layer properties layers of equal thickness were deposited. In order to do this the deposition rates first had to be established experimentally. When the SiH4WF6 ratio was maintained constant at 1 and the deposition temperature increased the resistivity of the layers decreases, and the roughness increased significantly. When the temperature was maintained constant at 450 °C and the SiH4WF6 ratio was varied, it was found that the resistivity remained constant until the tungsten transformed to beta phase tungsten. At this transformation point the stress of the deposited layer and the roughness were seen to decrease significantly. It was found when the correct chemistry was applied at deposition temperatures up to 400 °C the initial reaction between the WF6 and the Ti could be eliminated or reduced.

SiGe Heterojunction Bipolar Transistors on Insulating Substrates

This paper reviews progress in SiGe HBT technology as well as work on Si bipolar transistors on insulator (SOI) along with current work on SiGe HBTs on SOI. The state-of-the-art results on self-aligned selective epitaxially grown SiGe HBTs and SiGe:C HBTs clearly indicate the extendibility of these technologies into high-speed wired communication applications. Special emphasis is put on Silicon-on-Insulator HBT devices in vertical and lateral design. Research work on SOI SiGe HBT technology by a UK consortium has come up with a number of novel solutions, which are outlined. Moreover, issues regarding SOI operation in harsh environments are discussed.

Silicon-on-insulator substrates with buried ground, planes (GPSOI)

Experimental s/sub 21/ transmission crosstalk studies have been conducted on silicon-on-insulator substrates with buried ground planes (GPSOIs) where a 2 /spl Omega/ per square metal-silicide buried ground plane existed between a 15 /spl Omega/-cm p-type silicon substrate and a 1 μm thick buried CVD oxide layer. Locally grounded transmission test structures fabricated on GPSOI were found to exhibit 20 dB increased crosstalk suppression compared to published data for high resistivity (200 /spl Omega/-cm) SOI substrates incorporating capacitive guard rings over a frequency range from 500 MHz to 50 GHz. This represents an order of magnitude improvement in crosstalk power suppression capability compared to existing state-of-the-art suppression techniques in silicon substrates.

Impact of buried oxide thickness and ground plane resistivity on substrate cross-talk in ground plane silicon-on-insulator (GPSOI) cross-talk suppression technology

The impact of changing the buried oxide thickness and the ground plane resistivity on the substrate cross-talk in ground plane silicon-on-insulator (GPSOI) cross-talk suppression technology is investigated. It is found that crosstalk increases with increasing oxide thickness for low resistivity ground planes but decreases with increasing oxide thickness for higher ground plane resistivities over certain frequency ranges. An optimum buried oxide thickness is identified.

Characterization of Rapid Melt Growth (RMG) Process for High Quality Thin Film Germanium on Insulator

2012, Volume 45, Issue 4, Pages 169-180. ECS Trans. Paul T. Baine, David Adley and Tatania S. Perova Nurfarina Zainal, S.J.Neil Mitchell, David W. McNeill, Micheal F. Bain, B.M. Armstrong, High Quality Thin Film Germanium on Insulator Characterization of Rapid Melt Growth (RMG) Process for service Email alerting click here box at the top right corner of the article or Receive free email alerts when new articles cite this article sign up in the

Long-Range Lateral Dopant Diffusion in Tungsten Silicide Layers

Novel diode test structures have been manufactured to characterize long-range dopant diffusion in tungsten silicide layers. A tungsten silicide to p-type silicon contact has been characterized as a Schottky barrier rectifying contact with a silicide work function of 4.8 eV. Long-range diffusion of boron for an anneal at 900degC for 30 min has been shown to alter this contact to become ohmic. Long-range diffusion of phosphorus with a similar anneal alters the contact to become a bipolar n-p diode. Bipolar diode action is demonstrated experimentally for anneal schedules of 30 min at 900deg C, indicating long-range diffusion of phosphorus ( ~ 38 mum). SIMS analysis shows dopant redistribution is adversely affected by segregation to the silicide/oxide interface. The concept of conduit diffusion has been demonstrated experimentally for application in advanced bipolar transistor technology.