B.M. Armstrong

Ultralow silicon substrate noise crosstalk using metal Faraday cages in an SOI technology

Ultralow substrate crosstalk is demonstrated using a novel metal Faraday cage isolation scheme in silicon-on-insulator technology. Over ten times reduction in crosstalk is demonstrated up to 10 GHz, compared to previously reported substrate crosstalk suppression technologies.

SiGe HBTs on bonded SOI incorporating buried silicide layers

A technology is described for fabricating SiGe heterojunction bipolar transistors (HBTs) on wafer-bonded silicon-on-insulator (SOI) substrates that incorporate buried tungsten silicide layers for collector resistance reduction or buried groundplanes for crosstalk suppression. The physical structure of the devices is characterized using cross section transmission electron microscopy, and the electrical properties of the buried tungsten silicide layer are characterized using sheet resistance measurements as a function of bond temperature. Possible contamination issues associated with the buried tungsten silicide layer are investigated by measuring the collector/base reverse diode tics. A resistivity of 50 /spl mu//spl Omega/cm is obtained for the buried silicide layer for a bond anneal of 120 min at 1000/spl deg/C. Collector/base reverse diode tics show a voltage dependence of approximately V/sup 1/2/, indicating that the leakage current is due to Shockley-Read-Hall generation in the depletion region. Fitting of the current-voltage tics gives a generation lifetime of 90 ns, which is as expected for the collector doping of 7 /spl times/ 10/sup 17/ cm/sup -3/. These results indicate that the buried tungsten silicide layer does not have a serious impact on junction leakage.

Very-shallow low-resistivity p + -n junctions for CMOS technology

Shallow p-n junctions 110 nm deep have been fabricated using rapid thermal diffusion from a spin-on oxide source. Surface concentrations greater than 3 × 10²⁰cm^-3are possible, with sheet resistivities less than 100 Ω/sq and a maximum reverse-bias leakage at 5 V of 3 nA.cm^-2. Results from 150-nm junctions are also given and are compared with BF<inf>2</inf>ion implantation.

Silicon-on-insulator substrates with buried tungsten silicide layer

Abstract Tungsten silicide layers can be incorporated into silicon-on-insulator (SOI) substrates produced by direct wafer bonding. The series resistance of collectors/drains in bipolar or smart-power circuits can be reduced to 2 Ω/sq. The out-diffusion of the buried implanted collector contact during the post-bond anneal can be eliminated by using rapid diffusivity of donors and acceptors in tungsten silicide subsequent to bond anneal. Optimisation of this process can provide better matching of vertical complementary bipolar transistors. A novel silicon-on-silicide-on-insulator structure is proposed for integrating p–i–n diodes with low loss coplanar wave-guide lines. This incorporates a polysilicon surface layer on the high resistivity handle wafer and a tungsten silicide back contact to the diode. CPW lines with microwave losses of 2 dB/cm have been obtained at 30 GHz. The incorporation of a tungsten silicide layer below the buried silicon dioxide layer can be used as a ground plane. A tungsten silicide ground plane used with a standard SOI test structures was found to increase the suppression of cross-talk by 20 dB in the frequency range 1–10 GHz. Other potential applications such as ground plane and double-gate MOSFETs are discussed.

Comparison of Si1−yCy films produced by solid-phase epitaxy and rapid thermal chemical vapour deposition

Abstract Thin Si 1− y C y films with a range of carbon contents have been prepared by both solid-phase epitaxy (SPE) and rapid thermal chemical vapour deposition (RTCVD) techniques. For SPE growth, layers with carbon levels of up to 1.6 at.% exhibit strong substitutional incorporation. For RTCVD growth, substitutional carbon incorporation is difficult to achieve at a growth temperature of 800 °C, but has been achieved in layers estimated to contain 2 at.% carbon at a growth temperature of 700 °C. These results indicate that strain-compensated growth of Si 1− x − y Ge x C y with a wide range of composition should be possible in the present RTCVD system at temperatures of approximately 700 °C.

Low-temperature crystallisation of amorphous-silicon films for the fabrication of thin-film transistors

Abstract This paper reports on the crystallisation of low-pressure chemical-vapour deposited (LPCVD) amorphous silicon films for obtaining large grain polycrystalline layers. TEM and SEM studies are presented for samples 0.05–0.2 μm thick deposited in the temperature range from 495°C to 635°C, the pressure range 0.15 to 1.0 Torr and annealed in the temperature range 510°C to 610°C. The average grain size of the crystallised films is a function of the film thickness, the deposition rate and temperature, and the annealing temperature. An average grain size of 600 nm has been obtained in 200 nm thick films deposited at 540°C and annealed for 72 h at 550°C. Plasma-enhanced CVD of silicon dioxide produced by the reaction of silane and nitrous oxide is examined for the production of device quality silicon dioxide. Self-aligned silicon gate TFTs were fabricated on crystallised silicon deposited at 540°C and annealed at 550°C.

Electrical characterization of dielectrically isolated silicon substrates containing buried metallic layers

Dielectrically isolated substrates containing buried highly conducting WSi/sub 2/ layers are characterized for the first time using MOS capacitors. The active silicon layer is approximately 3 /spl mu/m thick with a buried WSi/sub 2/ layer adjacent to the isolation layer. The buried metal forms the back contact of the capacitor and excellent MOS characteristics are observed. Minority carrier lifetimes in excess of 200 /spl mu/s were measured indicating the suitability of these substrates for use in device manufacture.

Comparative study of large grains and high-performance TFTs in low-temperature crystallized LPCVD and APCVD amorphous silicon films

The crystallization of undoped amorphous silicon films deposited by low-pressure and atmospheric-pressure chemical vapour deposition (LPCVD and APCVD) at temperatures ranging between 510 and 650 °C and subsequently annealed at temperatures between 510 and 700 °C, for different durations, have been studied by transmission electron microscopy (TEM). It is found that the grain size in these films is influenced by the deposition and annealing temperatures and also by the deposition rate and film thickness. Maximum grain size of approximately 6400 A has been obtained in LPCVD silicon films 2000 A thick deposited at 540 °C and annealed at 550 °C for 144 h, whereas APCVD silicon films deposited at 590 °C and annealed at 610 °C for 72 h produced a grain size of approximately 4100 A. At higher and lower deposition temperatures the grain size was found to be smaller. Self-aligned silicon-gate thin-film transistors (TFTs) have been made using these crystallized amorphous/polycrystalline silicon films deposited at different temperatures by LPCVD and APCVD techniques, using SiO2 grown thermally at 850 °C as a gate dielectric. Device properties in these TFTs depend upon the deposition temperature, and a mobility value of 26–28 cm2 V−1 s−1 has been observed in LPCVD silicon TFTs at a deposition temperature of 540 °C, whereas APCVD silicon TFTs deposited at 590 °C show a mobility value of only 10.5 cm2 V−1 s−1.

Silicon interconnects for millimetre wave circuits

Recently high resistivity silicon (HRS) has been reported as an alternative to Gallium Arsenide as a high frequency MMIC foundry material. By employing aluminium metallized high resistivity silicon as a multilayer low cost interconnect medium passive structure (eg antennas, filters etc) can be fabricated at microwave and millimetre wavelengths. This paper demonstrates that thin metallization of aluminium can yield acceptable performance as coplanar waveguide circuit interconnects and can be used for direct circuit realization. A circuit example of the use of 1 ¿m aluminium metallization for the patterning antenna resonator is described. Various measurement issues are elaborated including the problem of contact resistance due to oxidation of the aluminium metallization.

Fermi level de-pinning of aluminium contacts to n-type germanium using thin atomic layer deposited layers

Fermi-level pinning of aluminium on n-type germanium (n-Ge) was reduced by insertion of a thin interfacial dielectric by atomic layer deposition. The barrier height for aluminium contacts on n-Ge was reduced from 0.7 eV to a value of 0.28 eV for a thin Al2O3 interfacial layer (∼2.8 nm). For diodes with an Al2O3 interfacial layer, the contact resistance started to increase for layer thicknesses above 2.8 nm. For diodes with a HfO2 interfacial layer, the barrier height was also reduced but the contact resistance increased dramatically for layer thicknesses above 1.5 nm.