P. Coppens

An industrial process for 650V rated GaN-on-Si power devices using in-situ SiN as a gate dielectric

This paper reports on an industrial DHEMT process for 650V rated GaN-on-Si power devices. The MISHEMT transistors use an in-situ MOCVD grown SiN as surface passivation and gate dielectric. Excellent off-state leakage, on-state conduction and low device capacitance and dynamic Ron is obtained. Initial assessment of the intrinsic reliability data on the in-situ SiN is provided.

Development of a robust 50V 0.35 /spl mu/m based Smart Power Technology using trench isolation

This paper describes a new 0.35 /spl mu/m CMOS based smart power technology. The so-called I3T50 technology belongs to a series of intelligent interface technologies developed within AMI Semiconductor over the past years. This technology is suitable for applications up to 50 V, such as automotive, peripheral and consumer applications. Trench isolation is used to isolate the devices, substantially reducing the isolation area. The set of devices available within this technology consists of n-type and p-type CMOS and DMOS devices, bipolar transistors, a high voltage floating diode, passive components, OTP memory and a set of ESD protection structures. In the future, the technology will be extended also with a modular embedded flash memory.

On the impact of carbon-doping on the dynamic Ron and off-state leakage current of 650V GaN power devices

A strong positive correlation between dynamic Ron and the ionization of buffer traps by injection of electrons from the Si substrate is presented. By exploring different Carbon doping profiles in the epi layers, the substrate buffer leakage is substantially reduced, which in turns results in lower dynamic Ron. The traps in the epi structure are characterized by different electrical techniques such as drain current transient, on-the-fly trapping and ramped back-gating experiments.

Plasma-charging damage of floating MIM capacitors

In this paper, the mechanism of plasma-charging damage (PCD) of metal-insulator-metal (MIM) capacitors as well as possible protection schemes are discussed. A range of test structures with different antennas simulating interconnect layout variations have been used to investigate the mechanism of PCD of MIM capacitors. Based on the experimental results, two models are presented, describing the relation between the damage and the ratio of the area of the exposed antennas connected to the MIM capacitors plates. New design rules are proposed in order to predict and automatically flag possible PCD sites. Furthermore, layout solutions to reduce PCD are suggested.

Reliability assessment of deep trench isolation structures

An extensive investigation of the reliability of deep trench isolation structures upon reverse bias stress is performed. By using the variable base level charge pumping technique, it is shown that the degradation of the trench primarily originates from N/sub it/ formation at the inner trench corners. The reliability is improved by introducing cut corners.

AlGaN/GaN power device technology for high current (100+ A) and high voltage (1.2 kV)

This paper extends our 650V rated GaN device technology to current ratings in excess of 100A. For the first time, devices with single digit Ron values are reported. A record low value of 6mΩ is measured at 100A. The device technology is shown to be fully current collapse free, over the complete voltage and temperature window. Intrinsic reliability test data up to Vds=900V, and T=200°C is provided. In addition, by using a thicker GaN buffer, 20A rated GaN power devices up to 1.2kV are presented, with leakage current ~100nA. This is a first step to allow AlGaN/GaN power devices to compete with Si IGBTs and SiC MOSFETs.

A high-speed silicon FET for efficient DC-DC power conversion

A novel silicon device architecture for DC-DC power conversion is reported. Efficient switching at high frequencies (1-5 MHz) is achieved by simultaneously reducing gate charge, reverse capacitance, and gate resistance while still maintaining good on-state resistance and off-state breakdown voltage. Power efficiencies in excess of 88% were realized in a synchronous buck converter running at 1.3 MHz.

Deep trench isolation for a 50 V 0.35 /spl mu/m based smart power technology

This paper describes the development of a deep trench isolation module for a new 0.35 /spl mu/m CMOS based smart power technology as well-as some major devices taking advantage of the features offered. by this deep trench isolation. The so-called I3T50 technology belongs to the third generation of intelligent interface technologies developed within AMI Semiconductor over the past years. This newest technology is suitable for applications up to 50 V, such as automotive, peripheral, industrial and consumer applications. Trench isolation is used to isolate the devices, hereby substantially reducing the isolation area. A full device library has been released within this technology (n-type and p-type CMOS and DMOS devices, bipolar transistors, high voltage floating diodes, passive components, OTP memory and a set of ESD protection structures).

Charging damage in floating metal-insulator-metal capacitors

In this paper, charging induced damage (CID) to metal-insulator-metal capacitors (MIMC) is reported. The damage is caused by the build up of a voltage potential difference between the two plates of the capacitor. A simple logarithmic relation is discovered between the damage by this voltage potential and the ratio of the area of the exposed antennas connected to the plates of the MIMC. This function allows anticipation of damage in MIMC devices with long interconnects. The source of the damage is still the subject of further investigation.

Prevention of plasma induced damage on thin gate oxide of HDP oxide deposition, metal etch, Ar preclean processing in BEOL sub-half micron CMOS processing

In this paper a comparison is made of several PID measurement techniques. A novel mechanism of plasma induced damage (PID) by high density plasma (HDP) inter metal dielectric (IMD) deposition is proposed. Results of a design of experiment (DOE) on Ar preclean minimizing PID are presented. For metal etch, HDP etch is compared reactive ion etch and the impact of individual process steps are identified by specialized antenna structures. Measurement results of Charge Pumping (CP), breakdown voltage (V/sub bd/) and gate oxide leakage are correlating very well. For HDP oxide deposition, plasma damage is minimal, assuring minimal exposure time of the metal line to the plasma using maximal deposition to sputter ratio. This process is inducing less PID than the classic SOG processing. Ar preclean induces minimal plasma damage using minimal process time, high ion energy and high plasma power. On metal etch, reactive ion etch is inducing less plasma damage then HDP etching. For both reactors PID is induced only in the metal over etch step.