Piet Vanmeerbeek

An industrial process for 650V rated GaN-on-Si power devices using in-situ SiN as a gate dielectric

This paper reports on an industrial DHEMT process for 650V rated GaN-on-Si power devices. The MISHEMT transistors use an in-situ MOCVD grown SiN as surface passivation and gate dielectric. Excellent off-state leakage, on-state conduction and low device capacitance and dynamic Ron is obtained. Initial assessment of the intrinsic reliability data on the in-situ SiN is provided.

Temperature-Dependent Dynamic

This paper reports an investigation of the trapping mechanisms responsible for the temperature-dependent dynamic-RON of GaN-based metal-insulator-semiconductor (MIS) high electron mobility transistors (HEMTs). More specifically, we perform the following. First, we propose a novel testing approach, based on combined OFF-state bias, backgating investigation, and positive substrate operation, to separately investigate the buffer-and the surface-related trapping processes. Then, we demonstrate that the dynamic RON of GaN-based MIS-HEMTs significantly increases when the devices are operated at high temperature levels. We explain this effect by demonstrating that it is due to the increased injection of electrons from the substrate to the buffer (under backgating conditions) and from the gate to the surface (under positive substrate operation). Finally, we demonstrate that by optimizing the buffer and by reducing the vertical leakage, substrate-related trapping effects can be completely suppressed. The results described within this paper provide general guidelines for the evaluation of the origin of dynamic RON in GaN power HEMTs and point out the important role of the buffer leakage in favouring the trapping processes.

R_{\mathrm {\mathrm{{\scriptstyle ON}}}}

A strong positive correlation between dynamic Ron and the ionization of buffer traps by injection of electrons from the Si substrate is presented. By exploring different Carbon doping profiles in the epi layers, the substrate buffer leakage is substantially reduced, which in turns results in lower dynamic Ron. The traps in the epi structure are characterized by different electrical techniques such as drain current transient, on-the-fly trapping and ramped back-gating experiments.

in GaN-Based MIS-HEMTs: Role of Surface Traps and Buffer Leakage

The role of buffer traps (identified as CN acceptors through current DLTS) in the off-state leakage and dynamic Ron of 650V rated GaN-on-Si power devices is investigated. The dynamic Ron is strongly voltage-dependent, due to the interplay between the dynamic properties of the CN traps and the presence of space-charge limited current components. This results in a complete suppression of dyn Ron degradation under HTRB conditions between 420V and 850V.

On the impact of carbon-doping on the dynamic Ron and off-state leakage current of 650V GaN power devices

A planar multiple floating field-limiting ring structure, designed for above 600V blocking capability, is analyzed in this work. We have proven by simulation and experiment that adding a well designed buffer layer in the epi-substrate region counteracts on the drop in electric field which is due to the space charge limited current and as such the buffer enhances the robustness towards reverse voltage biasing.

Impact of buffer leakage on intrinsic reliability of 650V AlGaN/GaN HEMTs

This paper presents an analysis of the high voltage trapping processes that take place in high-electron mobility transistors based on GaN, with a metal–insulator–semiconductor (MIS) structure. The study is based on combined pulsed and transient measurements, carried out with trapping voltages in the range from 50 to 500 V. The results indicate that: (i) dynamic Ron is maximum for trapping voltages between 200 and 300 V, and decreases for higher voltage levels; (ii) Ron-transient measurements reveal the presence of a dominant trap with activation energy Ea1 = 0.93 eV and of a second trap with activation energy equal to Ea2 = 0.61 eV; (iii) the deep level transient spectroscopy (DLTS) signal associated to trap Ea1 is completely suppressed for high trapping voltages (VDS = 500 V). The results are interpreted by considering that the trap Ea1 is located in the buffer, and originates from CN defects. The exposure to high drain voltages may favor the depletion of such traps, due to a field-assisted de-trapping process or to the presence of vertical leakage paths.

Enhancing the robustness of a multiple floating field-limiting ring termination by introducing a buffer layer

In this work the maximum UIS energy capability (Eas) for High-Voltage (600V-900V) Planar and SuperJunction (SJ) power MOSFETs is analyzed through experiment, TCAD simulation and analytical modeling. A new theoretical approach considering a buried heat source is presented to accurately predict Eas values in a wide range of voltage capability and load inductor values.

High voltage trapping effects in GaN-based metal–insulator–semiconductor transistors

The electric field balancing in the guard-ring edge termination structure of 600 V class Super-Junction devices is studied. The relation of the lateral electric field across the racetrack structure and the robustness of the structure against avalanche currents is investigated through experimental data and TCAD simulations. It has been found that the electrical field must be substantially imbalanced to achieve good ruggedness. The effect of the P-ring dose on the electrical performances of punch-through PiN diodes is also investigated.

Energy limits for unclamped inductive switching in high-voltage planar and SuperJunction power MOSFETs

A new lateral insulated gate bipolar transistor (LIGBT) for junction-isolated technologies is presented. The nLIGBT is integrated in an existing smart power technology without changing any process layers. The technology has a 0.35-mum CMOS core and is extended with five process layers in order to handle up to 80 V. The drift region of the nLIGBT is completely surrounded by p+ regions, creating a very effective hole bypass or diverter structure. This yields an LIGBT with a very wide safe operating area. The device has a breakdown voltage of 75 V and is able to operate up to 47 V (dc) when the gate is fully open. Furthermore, this device turns off without current tail, resulting in extremely fast turn-off times, which are solely determined by the voltage-rise phase. A true competitor for the quasi-vertical n-type drain extended metal oxide semiconductor (nDEMOS) in this technology is created

Electric field unbalance for robust floating ring termination

A 2D TCAD-based approach is proposed to investigate the leakage current and breakdown regime of GaN/AlGaN/Si structures at different ambient temperatures. Deep-level traps originated by Carbon doping, impact-ionization generation and thermally activated Poole-Frenkel conduction have been modeled to assess the role of such physical mechanisms on the forward-bias leakage current. A good agreement with experimental data has been obtained by implementing conduction and valence mini-bands within the deeper transition layer created by conductive dislocation defects or by superlattice structures. A 2D isolation device has been investigated up to breakdown and, for the first time to our knowledge, we prove with 2D TCAD simulation that in GaN based devices both impact-ionization and Poole-Frenkel conduction effects must be taken into account to correctly match experimental data.