Herman Maes

A reliable approach to charge-pumping measurements in MOS transistors

A new and accurate approach to charge-pumping measurements for the determination of the Si-SiO2interface state density directly on MOS transistors is presented. By a careful analysis of the different processes of emission of electrons towards the conduction band and of holes towards the valence band, depending on the charge state of the interface, all the previously ill-understood phenomena can be explained and the deviations from the simple charge-pumping theory can be accounted for. The presence of a geometric component in some transistor configurations is illustrated and the influence of trapping time constants is discussed. Furthermore, based on this insight, a new technique is developed for the determination of the energy distribution of interface states in small-area transistors, without requiring the knowledge of the surface potential dependence on gate voltage.

New insights in the relation between electron trap generation and the statistical properties of oxide breakdown

In this paper it is demonstrated in a wide stress field range that breakdown in thin oxide layers occurs as soon as a critical density of neutral electron traps in the oxide is reached. It is proven that this corresponds to a critical hole fluence, since a unique relationship between electron trap generation and hole fluence is found independent of stress field and oxide thickness. In this way literature models relating breakdown to hole fluence or to trap generation are linked. A new model for intrinsic breakdown, based on a percolation concept, is proposed. It is shown that this model can explain the experimentally observed statistical features of the breakdown distribution, such as the increasing spread of the Q/sub BD/-distribution for ultrathin oxides. An important consequence of this large spread is the strong area dependence of the Q/sub BD/ for ultrathin oxides.

Consistent model for the hot-carrier degradation in n-channel and p-channel MOSFETs

A model is derived using the charge-pumping technique for the evaluation of the interface characteristics, in combination with the behavior of the drain and the substrate currents after degradation. For n-channel transistors the degradation is mainly caused by the generation of interface traps. Only in the region of hole injection (V/sub g/ approximately=V/sub t/) is the degradation dominated by the trapped holes, which mask the effect of the generated interface traps. The degradation of p-channel transistors, although completely different at first sight, occurs by the same mechanisms. For this case, the degradation is caused by trapped negative charge, which masks the influence of the interface traps. The latter are nevertheless generated in comparable amounts as in n-channel transistors. Based on these insights, improved procedures for accelerated-lifetime experiments are proposed for both channel types. Finally, the peculiar degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model. >

On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates

ldquoConventionalrdquo techniques and related capacitance-voltage characteristic interpretation were established to evaluate interface trap density on Si substrates. We show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions. It is possible to both under- and overestimate the interface trap density by more than an order of magnitude. Pitfalls jeopardizing capacitance-and conductance-voltage characteristic interpretation for alternative semiconductor MOS are elaborated. We show how the conductance method, the most reliable and widely used interface trap density extraction method for Si, can be adapted and made reliable for alternative semiconductors while maintaining its simplicity.

Origin of the threshold voltage instability in SiO 2 /HfO 2 dual layer gate dielectrics

The magnitude of the V/sub T/ instability in conventional MOSFETs and MOS capacitors with SiO/sub 2//HfO/sub 2/ dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO/sub 2//HfO/sub 2/ interface and in the bulk of the HfO/sub 2/ layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows. 1) A defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO/sub 2//HfO/sub 2/ interface by tunneling.

A consistent model for the thickness dependence of intrinsic breakdown in ultra-thin oxides

A consistent model for the intrinsic time dependent dielectric breakdown (TDDB) of thin oxides is introduced. This model links the existing anode hole injection and the electron trap generation models together and describes wearout as a hole induced generation of electron traps. Breakdown is defined as conduction via these traps from one interface to the other. Implementing the model in a simulator, the oxide thickness dependence of the Weibull slope of the Q/sub BD/-distribution is predicted, and, using the unique relationship between hole fluence and generated electron trap density, the decrease of the critical hole fluence with oxide thickness is explained.

Stress measurements in silicon devices through Raman spectroscopy: Bridging the gap between theory and experiment

The different steps that have to be taken in order to derive information about local mechanical stress in silicon using micro‐Raman spectroscopy experiments, including theoretical and experimental aspects, are discussed. It is shown that the calculations are in general less complicated when they are done in the axes system of the sample. For that purpose, the secular equation is calculated in the axes system [110], [−110], [001], which is important for microelectronics structures. The theory relating Raman mode shift with stress tensor components is applied using two analytical stress models: uniaxial stress and planar stress. The results of these models are fitted to data from micro‐Raman spectroscopy experiments on Si3N4/poly‐Si lines on silicon substrate. In this fit procedure, the dimensions of the laser spot and its penetration depth in the substrate are also taken into account.

Transient enhanced diffusion of boron in Si

On annealing a boron implanted Si sample at similar to800 degreesC, boron in the tail of the implanted profile diffuses very fast, faster than the normal thermal diffusion by a factor 100 or more. ...

Silicon-on-insulator 'gate-all-around' MOS device

The total-dose radiation hardness of MOS devices is roughly inversely proportional to the square of the thickness of the oxide layers in contact with the silicon. In SOI (silicon-on-insulator) devices, the silicon layer sits on an oxide layer of typically 400 nm. It is proposed that a thin, gate-quality oxide can be realized at the front as well as the back of the devices, which should greatly enhance the radiation hardness. Double-gate devices (i.e. the same gate at the front and the back of the device) have been shown to have, at least theoretically, interesting short-channel and high transconductance properties. The only reported realization of such a device used a complicated, highly non-planar process (vertical devices) and left one edge of the device in contact with a thick oxide, which can be detrimental to rad-hard performances. Fabrication processes and device performances are described.<<ETX>>

Micro-Raman study of stress distribution in local isolation structures and correlation with transmission electron microscopy

Stress in local isolation structures is studied by micro‐Raman spectroscopy. The results are correlated with predictions of an analytical model for the stress distribution and with cross‐sectional transmission electron microscopy observations. The measurements are performed on structures on which the Si3N4 oxidation mask is still present. The influence of the pitch of the periodic local isolation pattern, consisting of parallel lines, the thickness of the mask, and the length of the bird’s beak on the stress distribution are studied. It is found that compressive stress is present in the Si substrate under the center of the oxidation mask lines, with a magnitude dependent on the width of the lines. Large tensile stress is concentrated under the bird’s beak and is found to increase with decreasing length of the bird’s beak and with increasing thickness of the Si3N4 film.