P. M. Gammon

Modelling the inhomogeneous SiC Schottky interface

For the first time, the I-V-T dataset of a Schottky diode has been accurately modelled, parameterised, and fully fit, incorporating the effects of interface inhomogeneity, patch pinch-off and resistance, and ideality factors that are both heavily temperature and voltage dependent. A Ni/SiC Schottky diode is characterised at 2 K intervals from 20 to 320 K, which, at room temperature, displays low ideality factors (n   8), voltage dependent ideality factors and evidence of the so-called “thermionic field emission effect” within a T0-plot, suggest significant inhomogeneity. Two models are used, each derived from Tungs original interactive parallel conduction treatment of barrier height inhomogeneity that can reproduce these commonly seen effects in single temperature I-V traces. The first model incorporates patch pinch-off effects and produces accurate and reliable fits above around 150 K, and at current densities lower than 10−5 A cm−2. Outside this region, we show that resistive effects within a given patch are responsible for the excessive ideality factors, and a second simplified model incorporating these resistive effects as well as pinch-off accurately reproduces the entire temperature range. Analysis of these fitting parameters reduces confidence in those fits above 230 K, and questions are raised about the physical interpretation of the fitting parameters. Despite this, both methods used are shown to be useful tools for accurately reproducing I-V-T data over a large temperature range.

Micro and nano analysis of 0.2 Ω mm Ti/Al/Ni/Au ohmic contact to AlGaN/GaN

As GaN technology continues to gain popularity, it is necessary to control the ohmic contact properties and to improve device consistency across the whole wafer. In this paper, we use a range of submicron characterization tools to understand the conduction mechanisms through the AlGaN/GaN ohmic contact. Our results suggest that there is a direct path for electron flow between the two dimensional electron gas and the contact pad. The estimated area of these highly conductive pillars is around 5% of the total contact area.

Analysis of inhomogeneous Ge/SiC heterojunction diodes

In this article Schottky barrier diodes comprising of a n-n germanium-silicon carbide (Ge-SiC) heterojunction are electrically characterized Circular transmission line measurements prove that the nickel front and back contacts are Ohmic, isolating the Ge/SiC heterojunction as the only contributor to the Schottky behavior Current-voltage plots taken at varying temperature (IVT) reveal that the ideality factor (n) and Schottky barrier height (SBH) (Phi) are temperature dependent and that incorrect values of file Richardson constant (A**) are being produced, suggesting tin inhomogeneous barrier Techniques originally designed for metal-semiconductor SBH extraction are applied to the heterojunction results to extract values of Phi and A** that are independent of temperature. The experimental IVT data are replicated using the Tung model It is proposed that small areas, or patches, making Lip Only 3% of the total contact area will dominate the I-V results due to their low SBH of 1.033 eV The experimental IVT data are also analyzed statistically using the extracted values of Phi to build Lip a Gaussian distribution of barrier heights. Including the standard deviation and a mean SBH of 1.126 eV, Which Should be analogous to file SBH extracted from capacitance-voltage (C-V) measurements. Both techniques yield accurate values of A** for SiC. However, the C-V analysis did not correlate with the mean SBH as expected

Si/SiC bonded wafer: A route to carbon free SiO2 on SiC

This paper describes the thermal oxidation of Si/SiC heterojunction structures, produced using a layer-transfer process, as an alternative solution to fabricating SiC metal-oxide-semiconductor (MOS) devices with lower interface state densities (Dit). Physical characterization demonstrate that the transferred Si layer is relatively smooth, uniform, and essentially monocrystalline. The Si on SiC has been totally or partially thermally oxidized at 900–1150 °C. Dit for both partially and completely oxidized silicon layers on SiC were significantly lower than Dit values for MOS capacitors fabricated via conventional thermal oxidation of SiC. The quality of the SiO2, formed by oxidation of a wafer-bonded silicon layer reported here has the potential to realize a number of innovative heterojunction concepts and devices, including the fabrication of high quality and reliable SiO2 gate oxides.

Si/SiC heterojunctions fabricated by direct wafer bonding

The physical and electrical properties of Si/SiC heterojunctions formed by direct wafer bonding are presented. Atomic force microscopy (AFM) and imaging reveal an improved bonding quality when Si wafers are transferred to on-axis substrates as opposed to off-axis epitaxial layers. AFM analysis of the bonded wafer achieves a smoother surface when compared to molecular beam epitaxy-grown Si layers. A reduced roughness of only 5.8 nm was measured for bonded wafers. Current-voltage measurements were used to extract the rectifying characteristics of Si/SiC heterojunctions. These Si layers could lead to improved high quality and reliable SiO2 gate oxides

Silicon and the wide bandgap semiconductors, shaping the future power electronic device market

In this paper, the current state of the power electronic device market is reviewed in light of the increased challenge upon Si from the wide bandgap semiconductors SiC and GaN. It is suggested that for the next ten years Si will continue its dominance both at the low voltage, and at the high voltage, high current ends of the market. However, SiC in particular is most likely to make a robust challenge upon the 500-6.5 kV market, in application areas such as automotive and photovoltaic converters and in PFC power supplies. As materials issues such as defect densities and epitaxial layer thicknesses improve then the emergence of bipolar SiC devices could in 10-20 years see it challenge in the high voltage, high current end of the market also.

On the Ti3SiC2 metallic phase formation for robust p-type 4H-SiC ohmic contacts

This paper presents a detailed physical and electrical analysis of 4H-SiC ohmic contacts to p-type material, the main aim being to examine their ruggedness under high temperature conditions. XRD, FIB-TEM and SEM are techniques that have been utilized to examine the microstructure and interface properties respectively. A detailed physical study revealed the presence of a crystalline hexagonal Ti layer orientated in the same direction as the 4H-SiC epitaxial layer. This factor seems to be important in terms of electrical performance, having the lowest measured specific contact resistivity of 1x10-6 Ωcm2. We attribute this to the optimized formation of Ti3SiC2 at the metal/SiC interface. An initial high temperature study shows thermionic emission occurring across the metal/semiconductor junction.

Nanoscale investigation of AlGaN/GaN-on-Si high electron mobility transistors

AlGaN/GaN HEMTs are devices which are strongly influenced by surface properties such as donor states, roughness or any kind of inhomogeneity. The electron gas is only a few nanometers away from the surface and the transistor forward and reverse currents are considerably affected by any variation of surface property within the atomic scale. Consequently, we have used the technique known as conductive AFM (CAFM) to perform electrical characterization at the nanoscale. The AlGaN/GaN HEMT ohmic (drain and source) and Schottky (gate) contacts were investigated by the CAFM technique. The estimated area of these highly conductive pillars (each of them of approximately 20-50 nm radius) represents around 5% of the total contact area. Analogously, the reverse leakage of the gate Schottky contact at the nanoscale seems to correlate somehow with the topography of the narrow AlGaN barrier regions producing larger currents.

Interface characteristics of n-n and p-n Ge/SiC heterojunction diodes formed by molecular beam epitaxy deposition

In this article, we report on the physical and electrical nature of Ge/SiC heterojunction layers that have been formed by molecular beam epitaxy (MBE) deposition. Using x-ray diffraction, atomic force microscopy, and helium ion microscopy, we perform a thorough analysis of how MBE growth conditions affect the Ge layers. We observe the layers developing from independent islands at thicknesses of 100 nm to flat surfaces at 300 nm. The crystallinity and surface quality of the layer is shown to be affected by the deposition parameters and, using a high temperature deposition and a light dopant species, the layers produced have large polycrystals and hence a low resistance. The p-type and n-type layers, 300 nm thick are formed into Ge/SiC heterojunction mesa diodes and these are characterized electrically. The polycrystalline diodes display near ideal diode characteristics (n < 1.05), low on resistance and good reverse characteristics. Current-voltage (I-V) measurements at varying temperature prove that all the layers have two-dimensional fluctuations in the Schottky barrier height (SBH) due to inhomogeneities at the heterojunction interface. Capacitance-voltage analysis and the SBH size extracted from I-V analysis suggest strongly that interface states are present at the surface causing Fermi-level pinning throughout the bands. A simple model is used to quantify the concentration of interface states at the surface.

Gate traps inducing band-bending fluctuations on AlGaN/GaN heterojunction transistors

Here, using a frequency dependent conductance analysis, we map the parallel conductance vs gate bias/frequency and further analyze the slow and fast traps as a function of the Fermi level for different gate architectures of analogous AlGaN/GaN heterojunction transistors with Schottky and SiNx metal-insulator-semiconductor (MIS) gate. The density of interface traps (Dit)-MIS reducing Dit-, the characteristic trap constant and the variance of the band-bending (σs) have been investigated for slow and fast traps. Additional gate stress appears to have a notable effect on the MIS fast trap profile with σs increasing up to 2.5 kT/q.