Craig A. Fisher

Modelling the inhomogeneous SiC Schottky interface

For the first time, the I-V-T dataset of a Schottky diode has been accurately modelled, parameterised, and fully fit, incorporating the effects of interface inhomogeneity, patch pinch-off and resistance, and ideality factors that are both heavily temperature and voltage dependent. A Ni/SiC Schottky diode is characterised at 2 K intervals from 20 to 320 K, which, at room temperature, displays low ideality factors (n   8), voltage dependent ideality factors and evidence of the so-called “thermionic field emission effect” within a T0-plot, suggest significant inhomogeneity. Two models are used, each derived from Tungs original interactive parallel conduction treatment of barrier height inhomogeneity that can reproduce these commonly seen effects in single temperature I-V traces. The first model incorporates patch pinch-off effects and produces accurate and reliable fits above around 150 K, and at current densities lower than 10−5 A cm−2. Outside this region, we show that resistive effects within a given patch are responsible for the excessive ideality factors, and a second simplified model incorporating these resistive effects as well as pinch-off accurately reproduces the entire temperature range. Analysis of these fitting parameters reduces confidence in those fits above 230 K, and questions are raised about the physical interpretation of the fitting parameters. Despite this, both methods used are shown to be useful tools for accurately reproducing I-V-T data over a large temperature range.

An Evaluation of Silicon Carbide Unipolar Technologies for Electric Vehicle Drive-Trains

Voltage sourced converters (VSCs) in electric vehicle (EV) drive-trains are conventionally implemented by silicon Insulated Gate Bipolar Transistors (IGBTs) and p-i-n diodes. The emergence of SiC unipolar technologies opens up new avenues for power integration and energy conversion efficiency. This paper presents a comparative analysis between 1.2-kV SiC MOSFET/Schottky diodes and silicon IGBT/p-i-n diode technologies for EV drive-train performance. The switching performances of devices have been tested between -75 °C and 175 °C at different switching speeds modulated by a range of gate resistances. The temperature impact on the electromagnetic oscillations in SiC technologies and reverse recovery in silicon bipolar technologies is analyzed, showing improvements with increasing temperature in SiC unipolar devices whereas those of the silicon-bipolar technologies deteriorate. The measurements are used in an EV drive-train model as a three-level neutral point clamped VSC connected to an electric machine where the temperature performance, conversion efficiency and the total harmonic distortion is studied. At a given switching frequency, the SiC unipolar technologies outperform silicon bipolar technologies showing an average of 80% reduction in switching losses, 70% reduction in operating temperature and enhanced conversion efficiency. These performance enhancements can enable lighter cooling and more compact vehicle systems.

An Analysis of the Switching Performance and Robustness of Power MOSFETs Body Diodes: A Technology Evaluation

The tradeoff between the switching energy and electro-thermal robustness is explored for 1.2-kV SiC MOSFET, silicon power MOSFET, and 900-V CoolMOS body diodes at different temperatures. The maximum forward current for dynamic avalanche breakdown is decreased with increasing supply voltage and temperature for all technologies. The CoolMOS exhibited the largest latch-up current followed by the SiC MOSFET and silicon power MOSFET; however, when expressed as current density, the SiC MOSFET comes first followed by the CoolMOS and silicon power MOSFET. For the CoolMOS, the alternating p and n pillars of the superjunctions in the drift region suppress BJT latch-up during reverse recovery by minimizing lateral currents and providing low-resistance paths for carriers. Hence, the temperature dependence of the latch-up current for CoolMOS was the lowest. The switching energy of the CoolMOS body diode is the largest because of its superjunction architecture which means the drift region have higher doping, hence more reverse charge. In spite of having a higher thermal resistance, the SiC MOSFET has approximately the same latch-up current while exhibiting the lowest switching energy because of the least reverse charge. The silicon power MOSFET exhibits intermediate performance on switching energy with lowest dynamic latching current.

Enhanced field effect mobility on 4H-SiC by oxidation at 1500◦C

A novel 1500°C gate oxidation process has been demonstrated on Si face of 4H-SiC. Lateral channel metal-oxide-semiconductor-field-effect-transistors (MOSFETs) fabricated using this process have a maximum field effect mobility of approximately 40 cm\2 V-1 s-1 without post oxidation passivation. This is substantially higher than other reports of MOSFETs with thermally grown oxides (typically grown at the standard silicon temperature range of 1100-1200°C). This result shows the potential of a high temperature oxidation step for reducing the channel resistance (thus the overall conduction loss), in power 4H-SiC MOSFETs.

Impact of the Oxidation Temperature on the Interface Trap Density in 4H-SiC MOS Capacitors

Despite the material advantages of Silicon-Carbide (SiC), the on resistance of 4H-SiC metal-oxide-semiconductor transistors are severely degraded by high trap densities near the oxide/SiC interface (Dit). In this work, the effect of the oxidation ambient (oxygen flow rates of 0.05 l/min-2.5 l/min) and oxidation temperature (1200°C-1600°C) on the Dit is investigated. The Dit was reduced by up to an order of magnitude using a combination of a low oxygen flow rate and a high temperature. The Dit was extracted from capacitance-voltage measurements made on MOS capacitors.

On the Ti3SiC2 metallic phase formation for robust p-type 4H-SiC ohmic contacts

This paper presents a detailed physical and electrical analysis of 4H-SiC ohmic contacts to p-type material, the main aim being to examine their ruggedness under high temperature conditions. XRD, FIB-TEM and SEM are techniques that have been utilized to examine the microstructure and interface properties respectively. A detailed physical study revealed the presence of a crystalline hexagonal Ti layer orientated in the same direction as the 4H-SiC epitaxial layer. This factor seems to be important in terms of electrical performance, having the lowest measured specific contact resistivity of 1x10-6 Ωcm2. We attribute this to the optimized formation of Ti3SiC2 at the metal/SiC interface. An initial high temperature study shows thermionic emission occurring across the metal/semiconductor junction.

Nanoscale investigation of AlGaN/GaN-on-Si high electron mobility transistors

AlGaN/GaN HEMTs are devices which are strongly influenced by surface properties such as donor states, roughness or any kind of inhomogeneity. The electron gas is only a few nanometers away from the surface and the transistor forward and reverse currents are considerably affected by any variation of surface property within the atomic scale. Consequently, we have used the technique known as conductive AFM (CAFM) to perform electrical characterization at the nanoscale. The AlGaN/GaN HEMT ohmic (drain and source) and Schottky (gate) contacts were investigated by the CAFM technique. The estimated area of these highly conductive pillars (each of them of approximately 20-50 nm radius) represents around 5% of the total contact area. Analogously, the reverse leakage of the gate Schottky contact at the nanoscale seems to correlate somehow with the topography of the narrow AlGaN barrier regions producing larger currents.

Improved performance of 4H-SiC PiN diodes using a novel combined high temperature oxidation and annealing process

In this paper, the application of a novel combined high temperature thermal oxidation and annealing process to mesa-isolated epitaxial-anode 4H-SiC PiN diodes with thick (110 μm) drift regions is presented, the aim of which was to increase the carrier lifetime in the 4H-SiC. Diodes were fabricated using 4H-SiC material having undergone this process, which consisted of a thermal oxidation in dry pure O2 at 1550°C followed by an argon anneal at the same temperature. Forward current-voltage characterization showed that the oxidised/annealed samples typically showed around 15% lower forward voltage drop and around 40% lower differential on-resistance (at 100 A/cm2 and 25°C) compared to control sample PiN diodes, whilst reverse recovery tests indicated a carrier lifetime increase also of around 40%. These findings illustrate that the use of this process is a highly effective and efficient way of improving the electrical characteristics of high voltage 4H-SiC bipolar devices.

A study of temperature-related non-linearity at the metal-silicon interface

In this paper, we investigate the temperature dependencies of metal-semiconductor interfaces in an effort to better reproduce the current-voltage-temperature (IVT) characteristics of any Schottky diode, regardless of homogeneity. Four silicon Schottky diodes were fabricated for this work, each displaying different degrees of inhomogeneity; a relatively homogeneous NiV/Si diode, a Ti/Si and Cr/Si diode with double bumps at only the lowest temperatures, and a Nb/Si diode displaying extensive non-linearity. The 77–300 K IVT responses are modelled using a semi-automated implementation of Tungs electron transport model, and each of the diodes are well reproduced. However, in achieving this, it is revealed that each of the three key fitting parameters within the model display a significant temperature dependency. In analysing these dependencies, we reveal how a rise in thermal energy “activates” exponentially more interfacial patches, the activation rate being dependent on the carrier concentration at the patc...

High-Temperature Electrical and Thermal Aging Performance and Application Considerations for SiC Power DMOSFETs

The temperature dependence and stability of three different commercially-available unpackaged SiC Dmosfets have been measured. On-state resistances increased to 6 or 7 times their room temperature values at 350 °C. Threshold voltages almost doubled after tens of minutes of positive gate voltage stressing at 300 °C, but approached their original values again after only one or two minutes of negative gate bias stressing. Fortunately, the change in drain current due to these threshold instabilities was almost negligible. However, the threshold approaches zero volts at high temperatures after a high temperature negative gate bias stress. The zero gate bias leakage is low until the threshold voltage reduces to approximately 150 mV, where-after the leakage increases exponentially. Thermal aging tests demonstrated a sudden change from linear to nonlinear output characteristics after 24–100 h air storage at 300 °C and after 570–1000 h in N2 atmosphere. We attribute this to nickel oxide growth on the drain contact metallization which forms a heterojunction p-n diode with the SiC substrate. It was determined that these state-of-the-art SiC mosfet devices may be operated in real applications at temperatures far exceeding their rated operating temperatures.