V. A. Shah

Spin transport in germanium at room temperature

Spin-dependent transport is investigated in a Ni/Ge/AlGaAs junction with an electrodeposited Ni contact. Spin-polarised electrons are excited by optical spin orientation and are subsequently used to measure the spin dependent conductance at the Ni/Ge Schottky interface. We successfully demonstrate electron spin transport and electrical extraction from the Ge layer at room temperature.

Characterization and modeling of n-n Si/SiC heterojunction diodes

In this paper we investigate the physical and electrical properties of silicon layers grown by molecular beam epitaxy on 4H-SiC substrates, evaluating the effect of the Si doping, Si temperature deposition, and SiC surface cleaning procedure. Si∕SiC monolithic integration of Si circuits with SiC power devices can be considered as an attractive proposition and has the potential to be applied to a broad range of applications. X-ray diffraction and scanning electron microscopy are used to determine the Si crystal structure (cubic silicon) and morphology. I-V and C-V measurements are performed to evaluate the rectifying diode characteristics along with the Si∕SiC built-in potential and energy band offsets. In the last section, we propose that our Si∕SiC heteojunction diode current characteristics can be explained by an isojunction drift-diffusion and thermoionic emission model where the effect of doping concentration of the silicon layer and its conduction band offset with SiC is analyzed.

Modelling the inhomogeneous SiC Schottky interface

For the first time, the I-V-T dataset of a Schottky diode has been accurately modelled, parameterised, and fully fit, incorporating the effects of interface inhomogeneity, patch pinch-off and resistance, and ideality factors that are both heavily temperature and voltage dependent. A Ni/SiC Schottky diode is characterised at 2 K intervals from 20 to 320 K, which, at room temperature, displays low ideality factors (n   8), voltage dependent ideality factors and evidence of the so-called “thermionic field emission effect” within a T0-plot, suggest significant inhomogeneity. Two models are used, each derived from Tungs original interactive parallel conduction treatment of barrier height inhomogeneity that can reproduce these commonly seen effects in single temperature I-V traces. The first model incorporates patch pinch-off effects and produces accurate and reliable fits above around 150 K, and at current densities lower than 10−5 A cm−2. Outside this region, we show that resistive effects within a given patch are responsible for the excessive ideality factors, and a second simplified model incorporating these resistive effects as well as pinch-off accurately reproduces the entire temperature range. Analysis of these fitting parameters reduces confidence in those fits above 230 K, and questions are raised about the physical interpretation of the fitting parameters. Despite this, both methods used are shown to be useful tools for accurately reproducing I-V-T data over a large temperature range.

Ultra-high hole mobility exceeding one million in a strained germanium quantum well

In this paper, we report a Hall mobility of one million in a germanium two-dimensional hole gas. The extremely high hole mobility of 1.1 × 106 cm2 V−1 s−1 at a carrier sheet density of 3 × 1011 cm−2 was observed at 12 K. This mobility is nearly an order of magnitude higher than any previously reported. From the structural analysis of the material and mobility modeling based on the relaxation time approximation, we attribute this result to the combination of a high purity Ge channel and a very low background impurity level that is achieved from the reduced-pressure chemical vapor deposition growth method.

High Quality Strained Ge Epilayers on a Si0.2Ge0.8/Ge/Si(100) Global Strain-Tuning Platform

High structural quality, compressively strained Ge surface epilayers have been grown on Si(100) substrates of up to 200 mm diameter. The epitaxial growth by industrially compatible reduced pressure chemical vapor deposition proceeded uninterruptedly via an intermediate relaxed Si0.2Ge0.8/Ge buffer. In-depth characterization of the epilayers revealed a relatively smooth surface and a low threading dislocation density. The Ge layers were demonstrated to remain fully strained for thicknesses of more than 100 nm. The high quality of the material and flexibility to choose the Ge layer thickness over a wide range make these heterostructures very attractive for fabricating various electronic and photonic devices

Analysis of inhomogeneous Ge/SiC heterojunction diodes

In this article Schottky barrier diodes comprising of a n-n germanium-silicon carbide (Ge-SiC) heterojunction are electrically characterized Circular transmission line measurements prove that the nickel front and back contacts are Ohmic, isolating the Ge/SiC heterojunction as the only contributor to the Schottky behavior Current-voltage plots taken at varying temperature (IVT) reveal that the ideality factor (n) and Schottky barrier height (SBH) (Phi) are temperature dependent and that incorrect values of file Richardson constant (A**) are being produced, suggesting tin inhomogeneous barrier Techniques originally designed for metal-semiconductor SBH extraction are applied to the heterojunction results to extract values of Phi and A** that are independent of temperature. The experimental IVT data are replicated using the Tung model It is proposed that small areas, or patches, making Lip Only 3% of the total contact area will dominate the I-V results due to their low SBH of 1.033 eV The experimental IVT data are also analyzed statistically using the extracted values of Phi to build Lip a Gaussian distribution of barrier heights. Including the standard deviation and a mean SBH of 1.126 eV, Which Should be analogous to file SBH extracted from capacitance-voltage (C-V) measurements. Both techniques yield accurate values of A** for SiC. However, the C-V analysis did not correlate with the mean SBH as expected

An extremely high room temperature mobility of two-dimensional holes in a strained Ge quantum well heterostructure grown by reduced pressure chemical vapor deposition

An extremely high room temperature two-dimensional hole gas (2DHG) drift mobility of 4230 cm2 V−1 s−1 in a compressively strained Ge quantum well (QW) heterostructure grown by an industrial type RP-CVD technique on a Si(001) substrate is reported. The low-temperature Hall mobility and carrier density of this structure, measured at 333 mK, are 777000 cm2 V−1 s−1 and 1.9 × 1011 cm−2, respectively. These hole mobilities are the highest not only among the group-IV Si based semiconductors, but also among p-type III–V and II–VI ones. The obtained room temperature mobility is substantially higher than those reported so far for the Ge QW heterostructures and reveals a huge potential for further application of strained Ge QW in a wide variety of electronic and spintronic devices.

Strain dependence of electron-phonon energy loss rate in many-valley semiconductors

We demonstrate significant modification of the electron-phonon energy loss rate in a many-valley semiconductor system due to lattice mismatch induced strain. We show that the thermal conductance from the electron system to the phonon bath in strained n+Si, at phonon temperatures between 200 and 480 mK, is more than an order of magnitude lower than that for a similar unstrained sample.

Strain enhanced electron cooling in a degenerately doped semiconductor

Enhanced electron cooling is demonstrated in a strained-silicon/superconductor tunnel junction refrigerator of volume 40 μm3. The electron temperature is reduced from 300 mK to 174 mK, with the enhancement over an unstrained silicon control (300 mK–258 mK) being attributed to the smaller electron-phonon coupling in the strained case. Modeling and the resulting predictions of silicon-based cooler performance are presented. Further reductions in the minimum temperature are expected if the junction sub-gap leakage and tunnel resistance can be reduced. However, if only tunnel resistance is reduced, Joule heating is predicted to dominate.

Electrical isolation of dislocations in Ge layers on Si(001) substrates through CMOS-compatible suspended structures

Abstract Suspended crystalline Ge semiconductor structures are created on a Si(001) substrate by a combination of epitaxial growth and simple patterning from the front surface using anisotropic underetching. Geometric definition of the surface Ge layer gives access to a range of crystalline planes that have different etch resistance. The structures are aligned to avoid etch-resistive planes in making the suspended regions and to take advantage of these planes to retain the underlying Si to support the structures. The technique is demonstrated by forming suspended microwires, spiderwebs and van der Pauw cross structures. We finally report on the low-temperature electrical isolation of the undoped Ge layers. This novel isolation method increases the Ge resistivity to 280 Ω cm at 10 K, over two orders of magnitude above that of a bulk Ge on Si(001) layer, by removing material containing the underlying misfit dislocation network that otherwise provides the main source of electrical conduction.