P. Normandon

Cu Grain Growth in Damascene Narrow Trenches

Since the end of the last century, Cu damascene integration scheme has been the favoured choice for advanced interconnect technologies. Indeed, due to the lowest Cu bulk resistivity and to it higher resistance to electromigration, performances enhancement with respect to Al have been obtained. Nevertheless, dimensional scaling considerably reduces these performances. At line width below 150nm, grain size is usually measured around line dimension and thus decreases with down scaling. Moreover, columnar grain morphology perpendicular to line sidewall is frequently observed. This results in a large increase of Cu resistivity and in degradation of resistance to electromigration. Optimization of Cu microstructure in damascene architecture is then required. This is the topic of this work. Direct measurements of microstructure through electron microscopy (TEM, EBSD) and X ray diffraction methods are performed. Indirect measurement of grain size evolutions via resistivity characterization is done. Complementary grain growth simulations are performed using vertex method. It is observed that, depending on line dimension, anneal conditions and electrolyte, different type of microstructures are achieved. As expected, certainly due grain boundary pinning on sidewall, for long time anneal, a stable situation is reached. We evidence that Cu line microstructure results from an interaction between grain growth inside the trenches and grain growth in the Cu overburden. On one hand, for the larger lines, the grain size is directly related to the grain growth in the overburden, on the other hand, for the narrowest lines, interfaces limit the impact of this layer on the inline grain growth. A quantitative measurement of overburden microstructure extension in trenches is reported. It could be used to optimize the in-line microstructure with respect to resistivity and electromigration resistance.

Silicon thickness monitoring strategy for FD-SOI 28nm technology

The silicon thickness (Tsi) fluctuation monitoring on FD-SOI 28nm technology process is addressed by 2 different electrical characterization techniques. The first, capacitive, is adapted to within wafer variations and lot/wafer variations monitoring. The second, using the Idsat sensitivity to the Tsi in an addressable transistors array, allows to measure the local variations in the range of few tens of microns.

Analysis of process impact on local variability thanks to addressable transistors arrays

We designed an addressable transistors array to analyse local variability at the wafer scale. On FDSOI substrates, we measure no impact of the silicon thickness variations on short channel transistors, and demonstrate that the impact on large area transistors is no more visible when the Tsi is well controlled.