P. R. Mukund

Self-calibration of input-match in RF front-end circuitry

The input match of RF front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input pad. The proposed technique ascertains the input match frequency of the circuit by using a built-in self-test (BiST) structure, determines the frequency interval by which it needs to be shifted to restore it to the desired value, and then feeds back a digital word to the low-noise amplifier (LNA), which adaptively corrects its input-match in real-time. The circuitry presented in the paper offers the advantages of low power overheads (the circuits can be powered off when not in use), robustness, no requirements of digital signal processing cores or processors, and fast calibration times (less than 30 /spl mu/s). This proof of concept is demonstrated by designing a cascode LNA and the complete self-calibration circuit in IBM 0.25-/spl mu/m CMOS RF process.

A current sensor for on-chip, non-intrusive testing of RF systems

This paper discusses design of a current sensor suitable for on-chip testing of RF circuits. The proposed sensor detects supply current (Idd) variations, with minimal impact on the circuit performance. Bandwidth of the circuit is 3.4 GHz, with a constant gain of 31.7 dB. The sensor has been implemented in IBM-6RF, 0.25 /spl mu/ CMOS technology, with 2.5 V power supply and it offers the low real estate overhead and high dynamic range required for this application.

An ultra-fast, on-chip BiST for RF low noise amplifiers

This paper presents an ultra-fast built in self test (BiST) approach for RF low noise amplifiers. The technique uses test inputs of moderate precision and low overhead base-band circuitry to quantify various functional specifications in the LNA such as input/output match, power gain and linearity. The total self-test time for all these parameters is 15/spl mu/s, which is several orders of magnitude improvement over existing test techniques. The BiST circuitry described presents low real estate and power overheads and does not require the presence of DSP cores to achieve self-test. The technique has been demonstrated for a 1.9GHz cascode LNA designed in the 0.25 micron IBM 6RF process.

A current based self-test methodology for RF front-end circuits

This paper presents a critical step in the realization of a robust, low overhead, current-based Built-In Self-Test (BIST) scheme for RF front-end circuits. The proposed approach involves sampling the high frequency supply current drawn by the circuit under test (CUT) and using it to extract information about various performance metrics of the RF CUT. The technique has inherently high fault coverage and can handle soft faults, hard faults as well as concurrent faults because it shifts the emphasis from detecting individual faults, to quantifying all the significant performance specifications of the CUT. This work also presents the realization of an HF current monitor which is a critical component in the proposed architecture. The current monitor has then been interfaced with three standard RF front-end circuits; a Low noise amplifier, a Single Balanced Mixer and a Voltage controlled oscillator, while minimally impacting their performance. The extracted information has then been used to create a mapping between variations in CUT performance and the sensed current spectrum. The monitor circuit has been fabricated in the IBM 6 metal, RF CMOS process, with a gain of 24 db and bandwidth of 3.9 GHz.

Designing bulk-driven MOSFETs for ultra-low-voltage analogue applications

This paper presents the design of an n-type bulk-driven MOSFET which is intended to facilitate the scaling of analogue circuitry down to 0.7 V, the minimum supply voltage predicted for the end of bulk CMOS. The bulk-driven MOSFET design will be carried out in two parts using the design rules of a standard 90 nm bulk CMOS technology. First, the impact of gate oxide scaling will be investigated to see how the bulk transconductance behaves as the oxide thickness is varied. Results will indicate that the oxide scaling requirements of a MOSFET can be relaxed by 0.4 nm when the bulk is used as the input terminal rather than the gate. Second, by taking advantage of a larger oxide thickness, it will be shown that a delta-doped profile is capable of improving the intrinsic gain and cut-off frequency of a bulk-driven MOSFET by as much as 429% and 71%, respectively, when compared to a uniformly doped bulk-driven device consistent with the specifications of a 90 nm bulk CMOS process. Overall, the delta-doped bulk-driven MOSFET will exhibit a long-channel bulk-to-gate transconductance ratio equal to 0.51, compared to 0.27 in the uniformly doped device (the gate transconductance was the same in both devices). The new delta-doped design will also increase the bulk-driven-to-gate-driven cut-off frequency ratio to 0.095–0.492 for channel lengths ranging from 80–800 nm, which is a 16–34% improvement over the uniformly doped case. When used in a differential amplifier circuit, the delta-doped bulk-driven MOSFET was found to have a dc voltage gain 185% higher than that of a similar amplifier utilizing uniformly doped devices.

Amplifier gain enhancement with positive feedback

The use of positive feedback as a solution to maximum intrinsic gain degradation in scaled technologies is discussed. Criteria for increasing gain while keeping the system stable are derived in terms of a non-ideal amplifier model. The amplifier model, in an attempt to standardize positive feedback analysis on generic amplifiers, includes non idealities that traditional feedback theory does not, including finite input impedance and non-zero output impedance. This treatment shows that as amplifier open loop gain decreases, positive feedback can more readily be applied to increase that gain at a cost of a slightly more than one-to-one tradeoff with the amplifier bandwidth and minimal area overhead. This analysis shows that the concept of positive feedback is most useful in high bandwidth single stage amplifiers where gain is at a minimum. The theory is applied to a differential amplifier in 65 nm technology and is shown to increase the DC gain by more than 25 dB in silicon measurements.

Self-calibration of gain and output match in LNAs

Increasing process variations and tolerance limits with successive scaling, along with rising costs per design cycle have made the fault-tolerance paradigm pertinent in RFICs. Due to the high frequencies involved, traditional fault-tolerance methods used in digital and lower frequency analog circuits cannot be applied. This paper presents a non-intrusive and robust technique of self-calibrating the gain and output match of LNAs. It involves very low overheads and does not degrade circuit performance in any measurable way, in addition to ultra-fast calibration times (lower than 50 mus). We present simulation results of the system designed in the IBM 0.25 mum process

1/f noise synthesis model in discrete-time for circuit simulation

Flicker noise, popularly known as 1/f noise is a commonly observed phenomenon in semiconductor devices. To incorporate 1/f noise in circuit simulations, models are required to synthesize such noise in discrete time. This paper proposes a model based on the fact that 1/f processes belong to the class of statistically self-similar random processes. The model generates 1/f noise in the time domain (TD) with a simple white noise input and is parameterized by a quantity whose value can be adjusted to reflect the desired 1/f parameter, that is, the slope of the 1/f spectrum. It thus differs from most of the earlier modeling approaches, which were confined to the spectral domain. To verify fit between the model and actual 1/f noise measurements, experiments were conducted using discrete devices such as a PIN photodiode at various bias conditions and sampling frequencies. The noise synthesized by the model was found to provide a good match to the measurements. Furthermore, it is demonstrated that the proposed 1/f noise model can also be incorporated in circuit simulations as a noise current or noise voltage source, which was not feasible earlier with the conventional spectral domain representation. To validate the inclusion of 1/f noise in circuits as TD current or voltage, simulations were carried out on a CMOS ring oscillator and the clock jitter due to 1/f noise was investigated.

A compensation technique for transistor mismatch in current mirrors

A compensation technique to correct the mismatch in the current mirrors due to transistor process parameter variations is presented. The compensation is achieved by varying the drain voltage of the mirroring transistors. This method is implemented by just adding a single transistor, operating in the linear region at the drain of the mirroring transistor. The circuit is simulated for a threshold voltage mismatch of /spl plusmn/10%. The simulation results show that the percentage error in the mirrored currents reduced from 48% to 3% for a threshold voltage mismatch of +10% and from 70% to 10% for a threshold voltage mismatch of -10%, for a wide range of input current values. The affect of temperature on the performance of the circuit is studied. The power consumption with and without the compensation transistor is compared. The compensation technique is successfully implemented in a CMOS image sensor.

Effects of technology and dimensional scaling on input loss prediction of RF MOSFETs

In this paper, we present the impact of both process and dimensional scaling on input loss (S/sub 11/) prediction of MOSFETs at GHz frequencies. We study the distributed gate effect, the non-quasi static effect, and report a drop in the resistive component of S/sub 11/ for larger fingered devices at high frequencies (> 5 GHz). We identify the boundary at which such effects start dominating. A modification to the existing lumped model is presented that tracks this effect with high accuracy. The impact of oxide thickness on S/sub 11/ in the same process and across two different processes is also presented. The study was validated with the fabrication of an extensive set of RF dimensioned transistors in LSI Logics 0.18 /spl mu/m and 0.11 /spl mu/m processes, across five different wafers.