Tejasvi Das

Self-calibration of input-match in RF front-end circuitry

The input match of RF front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input pad. The proposed technique ascertains the input match frequency of the circuit by using a built-in self-test (BiST) structure, determines the frequency interval by which it needs to be shifted to restore it to the desired value, and then feeds back a digital word to the low-noise amplifier (LNA), which adaptively corrects its input-match in real-time. The circuitry presented in the paper offers the advantages of low power overheads (the circuits can be powered off when not in use), robustness, no requirements of digital signal processing cores or processors, and fast calibration times (less than 30 /spl mu/s). This proof of concept is demonstrated by designing a cascode LNA and the complete self-calibration circuit in IBM 0.25-/spl mu/m CMOS RF process.

An ultra-fast, on-chip BiST for RF low noise amplifiers

This paper presents an ultra-fast built in self test (BiST) approach for RF low noise amplifiers. The technique uses test inputs of moderate precision and low overhead base-band circuitry to quantify various functional specifications in the LNA such as input/output match, power gain and linearity. The total self-test time for all these parameters is 15/spl mu/s, which is several orders of magnitude improvement over existing test techniques. The BiST circuitry described presents low real estate and power overheads and does not require the presence of DSP cores to achieve self-test. The technique has been demonstrated for a 1.9GHz cascode LNA designed in the 0.25 micron IBM 6RF process.

Self-calibration of gain and output match in LNAs

Increasing process variations and tolerance limits with successive scaling, along with rising costs per design cycle have made the fault-tolerance paradigm pertinent in RFICs. Due to the high frequencies involved, traditional fault-tolerance methods used in digital and lower frequency analog circuits cannot be applied. This paper presents a non-intrusive and robust technique of self-calibrating the gain and output match of LNAs. It involves very low overheads and does not degrade circuit performance in any measurable way, in addition to ultra-fast calibration times (lower than 50 mus). We present simulation results of the system designed in the IBM 0.25 mum process

Effects of technology and dimensional scaling on input loss prediction of RF MOSFETs

In this paper, we present the impact of both process and dimensional scaling on input loss (S/sub 11/) prediction of MOSFETs at GHz frequencies. We study the distributed gate effect, the non-quasi static effect, and report a drop in the resistive component of S/sub 11/ for larger fingered devices at high frequencies (> 5 GHz). We identify the boundary at which such effects start dominating. A modification to the existing lumped model is presented that tracks this effect with high accuracy. The impact of oxide thickness on S/sub 11/ in the same process and across two different processes is also presented. The study was validated with the fabrication of an extensive set of RF dimensioned transistors in LSI Logics 0.18 /spl mu/m and 0.11 /spl mu/m processes, across five different wafers.

Sensitivity analysis for fault-analysis and tolerance in RF front-end circuitry

RFIC reliability is fast becoming a major bottleneck in the yield and performance of modern IC systems, as process complexity and levels of integration continually increase. Due to high frequencies involved, testing these chips is both complicated and expensive. While the areas of automated testing and self-test have received significant attention over the past few years, no formal framework of fault-models or sensitivity-models exists in the RF domain. This paper describes a sensitivity analysis methodology as a first step towards such a framework. It is applied towards a low noise amplifier, and a case-study application is discussed by using design and experimental results of an adaptive LNA designed in the IBM6RF 0.25 mum CMOS process

A low noise current-mode readout circuit for CMOS image sensing applications

A major obstacle in current-mode CMOS image sensors is the transconductance gain mismatch across pixels, which translates to Fixed Pattern Noise (FPN), degrading the image quality. In this paper, we propose a highly linear and compact current-mode readout circuit that eliminates this mismatch by performing the voltage to current conversion within a unity gain feedback loop. It is further proposed that by using the Active Column Sensor (ACS) architecture, only two transistors from the readout circuit are required to be present at the pixel site, while the rest of the circuitry resides common to an entire column. This setup saves a significant amount of real estate. The circuit is designed in TSMC 0.25 /spl mu/m process, and simulation results are presented.