Anand Gopalan

Self-calibration of input-match in RF front-end circuitry

The input match of RF front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input pad. The proposed technique ascertains the input match frequency of the circuit by using a built-in self-test (BiST) structure, determines the frequency interval by which it needs to be shifted to restore it to the desired value, and then feeds back a digital word to the low-noise amplifier (LNA), which adaptively corrects its input-match in real-time. The circuitry presented in the paper offers the advantages of low power overheads (the circuits can be powered off when not in use), robustness, no requirements of digital signal processing cores or processors, and fast calibration times (less than 30 /spl mu/s). This proof of concept is demonstrated by designing a cascode LNA and the complete self-calibration circuit in IBM 0.25-/spl mu/m CMOS RF process.

A current sensor for on-chip, non-intrusive testing of RF systems

This paper discusses design of a current sensor suitable for on-chip testing of RF circuits. The proposed sensor detects supply current (Idd) variations, with minimal impact on the circuit performance. Bandwidth of the circuit is 3.4 GHz, with a constant gain of 31.7 dB. The sensor has been implemented in IBM-6RF, 0.25 /spl mu/ CMOS technology, with 2.5 V power supply and it offers the low real estate overhead and high dynamic range required for this application.

An ultra-fast, on-chip BiST for RF low noise amplifiers

This paper presents an ultra-fast built in self test (BiST) approach for RF low noise amplifiers. The technique uses test inputs of moderate precision and low overhead base-band circuitry to quantify various functional specifications in the LNA such as input/output match, power gain and linearity. The total self-test time for all these parameters is 15/spl mu/s, which is several orders of magnitude improvement over existing test techniques. The BiST circuitry described presents low real estate and power overheads and does not require the presence of DSP cores to achieve self-test. The technique has been demonstrated for a 1.9GHz cascode LNA designed in the 0.25 micron IBM 6RF process.

A current based self-test methodology for RF front-end circuits

This paper presents a critical step in the realization of a robust, low overhead, current-based Built-In Self-Test (BIST) scheme for RF front-end circuits. The proposed approach involves sampling the high frequency supply current drawn by the circuit under test (CUT) and using it to extract information about various performance metrics of the RF CUT. The technique has inherently high fault coverage and can handle soft faults, hard faults as well as concurrent faults because it shifts the emphasis from detecting individual faults, to quantifying all the significant performance specifications of the CUT. This work also presents the realization of an HF current monitor which is a critical component in the proposed architecture. The current monitor has then been interfaced with three standard RF front-end circuits; a Low noise amplifier, a Single Balanced Mixer and a Voltage controlled oscillator, while minimally impacting their performance. The extracted information has then been used to create a mapping between variations in CUT performance and the sensed current spectrum. The monitor circuit has been fabricated in the IBM 6 metal, RF CMOS process, with a gain of 24 db and bandwidth of 3.9 GHz.

An ASIC-Ready 1.25–6.25Gb/s SerDes in 90nm CMOS with multi-standard compatibility

A small area PHY transceiver that is compatible with CE16G-LR, CE16G-SR, SAS-6G, PCle and XAUl standards is demonstrated. The 4-channel transceiver is realized in a 90 nm CMOS process with each channel occupying a die area of 0.325 mm2. Power dissipation per channel is less than 230 mW from a 1V supply for 6.25 Gb/s, and scales for data rates down to 1.25 Gb/s.

Passive and Active Reduction Techniques for On-Chip High-Frequency Digital Power Supply Noise

Signal integrity has become a major problem in digital IC design. One cause is device scaling that results in a sharp reduction of supply voltage, creating stringent noise margin requirements to ensure functionality. This paper introduces both a novel on-chip decoupling capacitance methodology and active noise cancellation (ANC) structure. The decoupling methodology focuses on quantification and location. The ANC structure, with an area of 50 ¿m × 55 ¿m, uses decoupling capacitance to sense noise and inject a proportional current into VSS as a method of reduction. A chip has been designed and fabricated using TSMCs 90-nm technology. Measurements show that the decoupling methodology improved the average voltage headroom loss by 17% while the ANC structure improved the average voltage headroom loss by 18%.

Generalized design of diffractive optical elements using neural networks

Diffractive optical elements (DOE) utilize diffraction to manipulate light in optical systems. These elements have a wide range of applications including optical interconnects, coherent beam addition, laser beam shaping and refractive optics aberration correction. Due to the wide range of applications, optimal design of DOE has become an important research problem. In the design of the DOEs, existing techniques utilize the Fresnel diffraction theory to compute the phase at the desired location at the output plane. This process involves solving nonlinear integral equations for which various numerical methods along with robust optimization algorithms exist in literature. However all the algorithms proposed so far assume that the size and the spacing of the elements as independent variables in the design of optimal diffractive gratings. Therefore search algorithms need to be called every time the required geometry of the elements changes, resulting in a computationally expensive design procedure for systems utilizing a large number of DOEs. In this work we have developed a novel algorithm that uses neural networks with possibly multiple hidden layers to overcome this limitation and arrives at a general solution for the design of the DOEs for a given application. Inputs to this network are the spacing between the elements and the input/output planes. The network outputs the phase gratings that are required to obtain the desired intensity at the specified location in the output plane. The network was trained using the back-propagation technique. The training set was generated by using GS algorithm approach as described in literature. The mean square error obtained is comparable to conventional techniques but with much lower computational costs.