Clyde Washburn

Self-calibration of input-match in RF front-end circuitry

The input match of RF front-end circuitry can degrade significantly due to process faults and parasitic package inductances at its input pad. The proposed technique ascertains the input match frequency of the circuit by using a built-in self-test (BiST) structure, determines the frequency interval by which it needs to be shifted to restore it to the desired value, and then feeds back a digital word to the low-noise amplifier (LNA), which adaptively corrects its input-match in real-time. The circuitry presented in the paper offers the advantages of low power overheads (the circuits can be powered off when not in use), robustness, no requirements of digital signal processing cores or processors, and fast calibration times (less than 30 /spl mu/s). This proof of concept is demonstrated by designing a cascode LNA and the complete self-calibration circuit in IBM 0.25-/spl mu/m CMOS RF process.

An ultra-fast, on-chip BiST for RF low noise amplifiers

This paper presents an ultra-fast built in self test (BiST) approach for RF low noise amplifiers. The technique uses test inputs of moderate precision and low overhead base-band circuitry to quantify various functional specifications in the LNA such as input/output match, power gain and linearity. The total self-test time for all these parameters is 15/spl mu/s, which is several orders of magnitude improvement over existing test techniques. The BiST circuitry described presents low real estate and power overheads and does not require the presence of DSP cores to achieve self-test. The technique has been demonstrated for a 1.9GHz cascode LNA designed in the 0.25 micron IBM 6RF process.

Effects of technology and dimensional scaling on input loss prediction of RF MOSFETs

In this paper, we present the impact of both process and dimensional scaling on input loss (S/sub 11/) prediction of MOSFETs at GHz frequencies. We study the distributed gate effect, the non-quasi static effect, and report a drop in the resistive component of S/sub 11/ for larger fingered devices at high frequencies (> 5 GHz). We identify the boundary at which such effects start dominating. A modification to the existing lumped model is presented that tracks this effect with high accuracy. The impact of oxide thickness on S/sub 11/ in the same process and across two different processes is also presented. The study was validated with the fabrication of an extensive set of RF dimensioned transistors in LSI Logics 0.18 /spl mu/m and 0.11 /spl mu/m processes, across five different wafers.

Analog IC Design in Ultra-Thin Oxide CMOS Technologies With Significant Direct Tunneling-Induced Gate Current

Recent studies have shown that manufacturing costs and design complexities may delay the widespread use of high-κ/metal gate nanoscale CMOS technologies. This implies that traditional (non-high-κ/non-metal gate) ultra-thin oxide technologies will remain active due to economic factors for longer periods of time. Direct tunneling is a significant source of MOSFET gate current in these technologies. Its presence fundamentally alters MOSFET functionality by invalidating the simplifying design assumption of infinite gate resistance. Analog circuit solutions to its problems do not exist in the literature. This paper proposes design solutions that attempt to minimize, balance, and cancel the negative effects of direct tunneling on analog design in traditional ultra-thin oxide CMOS technologies. The proposed solutions re quire only ultra-thin oxide devices and are investigated in a 65-nm CMOS technology with a nominal VDD of 1 V and a physical oxide thickness of 1.25 nm.

An analytical propagation delay model with power supply noise effects

This paper presents an analytical model for CMOS logic propagation delay which includes the effect of power supply noise. Using the nth power law model of MOSFETs, two scenarios are addressed: self-induced power supply noise and globally-induced power supply noise. The analytical model is verified in simulation for both cases. The self-induced noise model matches simulation to within 0.36%. The globally-induced noise model matches simulation to within 5% for typical input rise time values and never more than 15% under extreme conditions

Accurate performance prediction of multi-GHz CML with data run-length variations

Accurate prediction of multi-GHz CML dependency on data run-time variation requires precise device models at those frequencies. Inconsistencies caused in the CML by run-time variations of the input data are clearly demonstrated. Further, an accurate RF MOSFET model that can be dynamically changed to adapt to the input data stream variations is implemented. This model is used to simulate a CML buffer, where symmetrical and asymmetrical variations in the data stream run-length are considered. The simulation results show that the data run-length variations can degrade the buffer output by as much as 40%.

An ultra-thin oxide sub-1 V CMOS bandgap voltage reference

This paper presents a sub-1 V CMOS bandgap voltage reference that accounts for the presence of direct tunneling-induced gate current. This current increases exponentially with decreasing oxide thickness and is especially prevalent in traditional non-high-i¾?/metal gate ultra-thin oxide CMOS technologies tox<3 nm, where it invalidates the simplifying design assumption of infinite gate resistance. The developed reference average temperature coefficient, TC_AVG, of 22.5 ppm/i¾?C overcomes direct tunneling by employing circuit techniques that minimize, balance, and cancel its effects. It is compared to a thick-oxide voltage reference TC_AVG=14.0 ppm/i¾?C as a means of demonstrating that ultra-thin oxide MOSFETs can achieve performance similar to that of more expensive thicker oxide MOSFETs and that they can be used to design the analog component of a mixed-signal system. The reference was investigated in a 65 nm CMOS technology with a nominal VDD of 1 V and a physical oxide thickness of 1.25 nm. Copyright

A universal common-source and common-drain model for 1-20GHz frequency range

Extraction plays an important role in the performance of device models especially in the high frequency regime. The present day extraction techniques mostly use a grounded source or common source (CS) device configuration. The models extracted from the grounded source devices are then used for devices in other configurations in a circuit application. This leads to discrepancies in accurate prediction of the circuit performance. This work investigates, the applicability of the models extracted using CS for other device configurations. It was shown with the help of measured data, in the frequency range of 1-20 GHz, that the models extracted from CS configuration do not predict the performance of a device in common drain (CD) configuration. Based on the above observation, a universal gate impedance model that works for both CS and CD configurations for BSIM3v3 was developed. The gate impedance model was then extended to BSIM4 for both CS and CD configurations. The models for BSIM3v3 and BSIM4 are verified using simulations and compared with the measured data

Effect of gate poly-silicon depletion on MOSFET input impedance

One of the most challenging problems encountered in developing RF circuits is accurate prediction of MOS behavior at microwave signal and data frequencies. An attempt is made in this work to accurately model the device input impedance for the 1-20-GHz frequency range. The effect of device length and single-leg width on the input impedance is studied with the aid of extensive measured data obtained from devices built in 0.11-/spl mu/m and 0.18-/spl mu/m technologies. The measured data illustrates that the device input impedance has a nonlinear frequency dependency. It is also shown that this variation in input impedance is a result of gate poly-silicon depletion, which can be modeled by an external RC network connected at the gate of the device. Excellent agreement between the simulation results and the measured data validates the model in the device active region.