Jean-Michel Fournier

A Low Power Inductorless LNA With Double

This paper presents the design of a low power differential Low Noise Amplifier (LNA) in 130 nm CMOS technology for 2.45 GHz ISM band applications. The circuit benefits from several gm-enhancements. These techniques provide a high gain and reduced Noise Figure (NF) in spite of the low intrinsic gm of the MOS transistors. Moreover, the circuit is fully inductorless. Main design points are described and the performance tradeoffs of the circuit are discussed. A prototype has been implemented and it exhibits a 20 dB gain with a 4 dB NF while dissipating 1.32 mW. The IIP3 is -12 dBm for an input compression point of -21 dBm.

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A millimeter-wave power amplifier (PA) implemented in a 65 nm CMOS process with 8-metal layers and transistor fT/fMAX of 160/200 GHz is reported. The PA operates from a 1.2 V supply voltage. A power gain of 13.4 dB, an output P1dB of 12.2 dBm with 7.6 % PAE and a saturated output power of 13.8 dBm at 58 GHz are measured. S11 and S22 are lower than 10 dB, which ensures an input and output matching to a 50 ¿ impedance. These results are obtained thanks to accurate millimeter wave models for MOS and integrated microstrip lines used as passive components. The amplifier design takes electromigration constraints at 105°C into account. Excellent agreement between measurement and simulation results is observed.

Enhancement in 130 nm CMOS

The effects of RF hot-carrier stress on the characteristics of 60-GHz power amplifiers (PAs) on a CMOS 65-nm process are investigated, for the first time, in this letter. A reliability study is made on a one-stage PA to validate an aging model and the degradation explanation. A drop of 16% of the gain, 17% of the 1-dB output compression point (<i>OCP</i>_{1 dB}), and 17% of the <i>P</i>_sat are measured at 60 GHz after 50 h of stress under <i>V</i>_dd = 1.65 V with <i>P</i>_in = 0 dBm and <i>V</i>_dd = 1.9 V with <i>P</i>_in = -10 dBm at 60-GHz frequency.

A CMOS class-A 65nm power amplifier for 60 GHz applications

This paper presents the application of the state space approach to analyze stability and robustness of multiloop linear low dropout (LDO) regulators. Because of the increasing complexity of the LDO architecture, the stability study consisting of an open-loop ac analysis is more and more difficult to apply. In this paper, we demonstrate how a state matrix decomposition of a system allows the stability analysis in closed loop to be performed where the open-loop ac analysis failed. Based on this technique, a methodology of design, a time response criterion, and a Monte Carlo analysis are proposed. The efficiency of this approach is illustrated comparing the classical open-loop ac study with the state matrix decomposition analysis of a complex innovative architecture LDO. The results are verified experimentally.

Hot-Carrier Stress Effect on a CMOS 65-nm 60-GHz One-Stage Power Amplifier

A hot carrier ageing model previously validated on a one-stage 60-GHz power amplifier (PA) is demonstrated to be able to predict the degradation of the characteristic parameters for multistage high-performance millimeter-wave (mmW) PAs. The increase in the threshold voltage, the decrease in the transconductance, and the output conductance of the MOSFETs caused by hot carriers leads to a degradation in performance of the PAs. Consequently, by using this ageing model, the mmW PA lifetime can be extracted. A new PA is then designed, taking into account the ageing effects, and is shown to be reliable during ten years. This amplifier exhibits a power gain of 20 dB, an output 1-dB compression point of 12.5 dBm with 6.6% power-added efficiency, and a saturated output power of 16 dBm at 60 GHz.

Stability Analysis and Design Procedure of Multiloop Linear LDO Regulators via State Matrix Decomposition

This paper presents an inductorless low power (LP) low noise amplifier (LNA) based on a Common Gate (CG) topology. The circuit combines gain boosting techniques to enable high gain LP LNA. The circuit is integrated in a 130nm CMOS technology and shows 20dB gain with 4dB Noise Figure and −12dBm IIP3. The power consumption is 1.32mW from a 1.2V supply.

Design-in-Reliable Millimeter-Wave Power Amplifiers in a 65-nm CMOS Process

The effects of dc hot carrier stress on the characteristics of 60GHz power amplifiers on CMOS 65nm are investigated. The increase in the threshold voltage, the decrease in the transconductance and the output conductance of the MOSFETs caused by hot carriers leads to a loss performances of the PAs. A reliability study is first made on a 1 stage PA to validate the ageing model and the degradation explanation. A drop of 5% the gain, 7% of the OCP1dB, 7% of the Psat are measured at 58GHz after 50 hours of stress under Vdd=1.7V on a 4 stages amplifier.

A 1.3mW 20dB gain low power inductorless LNA with 4dB Noise Figure for 2.45GHz ISM band

In this letter, a traveling-wave single-pole double-throw (SPDT) switch using slow-wave coplanar waveguides is implemented in a 65-nm triple-well CMOS process. For performance improvement, double-well body-floating technique is used. The p-well layer and deep n-well layer of nMOSFET being, respectively, biased to -1.4 and 2.0 V, the measured SPDT exhibits an insertion loss of 2.8 dB and an isolation of 20 dB at 60 GHz. A measured input 1-dB compression point (ICP1dB) of 17 dBm is obtained at 35 GHz (16.3 dBm at 60 GHz by simulation). The total chip size is only 0.42 mm2 (780 μm× 540 μm) including all testing pads.

DC hot carrier stress effect on CMOS 65nm 60 GHz power amplifiers

A millimeter-wave frequency quadrupler implemented in BiCMOS 55 nm process from STMicroelectronics for in situ load-pull D band characterization is proposed. The circuit consists on cascaded doublers with intermediate power amplifiers to increase the output power. Two high-pass filters allow the rejection of the first and 2nd harmonics to obtain pure 4th harmonic output frequency. The measured peak output power is 0.5 dBm at 150 GHz with 14 GHz 3dB bandwidth and a DC power consumption of 0.63W. A good agreement between measurement and simulation results is observed.

A Traveling-Wave CMOS SPDT Using Slow-Wave Transmission Lines for Millimeter-Wave Application

An improved analytical model for integrated microstrip line experienced on 45 nm silicon technology is proposed. This model is derived from previous classical ones used for PCB circuits. Improvements have been performed to take into account the sizing effects for integrated lines. The study is performed up to 110 GHz for different line widths and results accuracy allow implementing the model in CAD software like Eldo, Spectre and the Agilent tools (RFDE, ADS, and GoldenGate) for mm-wave designs.