P. Sivasubramani

Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning

An interface dipole model explaining threshold voltage (Vt) tuning in HfSiON gated n-channel field effect transistors (nFETs) is proposed. Vt tuning depends on rare earth (RE) type and diffusion in Si∕SiOx∕HfSiON∕REOx/metal gated nFETs as follows: Sr<Er<Sc+Er<La<Sc<none. This Vt ordering is very similar to the trends in dopant electronegativity (EN) (dipole charge transfer) and ionic radius (r) (dipole separation) expected for a interfacial dipole mechanism. The resulting Vt dependence on RE dopant allows distinction between a dipole model (dependent on EN and r) and an oxygen vacancy model (dependent on valence).

Higher permittivity rare earth doped HfO2 for sub-45-nm metal-insulator-semiconductor devices

Rare earth (RE) doping (Gd, Er, Dy) of HfO2 reduces leakage current by three orders of magnitude compared with pure HfO2. The key to reducing HfO2 leakage current and equivalent oxide thickness (EOT) is stabilization of the higher permittivity tetragonal phase. RE doping of 10–20at.% stabilizes tetragonal HfO2 and increases permittivity. The maximum permittivity achieved for HfREOx is 28. The maximum permittivity for ZrREO is 32. HfGdO metal-insulator-semiconductor capacitors with EOT=1.93nm and leakage current <1×10−8A∕cm2 after 1070°C have been demonstrated.

Dipole Moment Model Explaining nFET V t Tuning Utilizing La, Sc, Er, and Sr Doped HfSiON Dielectrics

A dipole moment model explaining Vt tuning in HfSiON gated nFETs is proposed and its impact on performance and reliability is presented. La, Sc, Er, and Sr dopants are utilized due to their differing electronegativities and ionic radii. These dopants tune Vt in the range of 250-600 mV. Vt tuning is found to be proportional to the net dipole moment associated with the Hf-O and rare earth (RE)-O bonds at the high-k/SiO2 interface. The magnitude of this interfacial dipole moment is determined by the electronegativities and ionic radii of the RE cations. LaOx is the most effective dopant based on Vt, mobility, and reliability,

Mechanisms limiting EOT scaling and gate leakage currents of high-k/metal gate stacks directly on SiGe and a method to enable sub-1nm EOT

For the first time, we provide mechanistic understanding of high gate leakage current on surface channel SiGe pFET with high-k/metal gate to enable sub 1 nm EOT. The primary mechanism limiting EOT scaling is Ge enhanced Si oxidation resulting in a thick (1.4 nm) SiOx interface layer. A secondary mechanism, Ge doping (ges4%) in high-k, possibly by up diffusion, also results in higher leakage. With this understanding, we optimized high-k nitridation reducing O and Ge diffusion to achieve EOT=0.91 nm directly on SiGe with leakage equivalent to bulk Si. High Ion (1.5times Si), and low subthreshold slope (73 mV/dec) are also achieved. This mechanism enables high mobility channel gate dielectric development directly on SiGe without the need for Si cap, simplifying processing and device design.

The impact of la-doping on the reliability of low Vth high-k/metal gate nMOSFETs under various gate stress conditions

La-doped HfSiO samples show lower threshold voltage (Vth) and gate current (Igate), which is attributed to dipole formation at the high-k/SiO2 interface. At low and intermediate field stress, La-doped devices exhibit better immunity to positive bias temperature instability (PBTI) due to their lower charge trapping efficiency than the control HfSiO, which mainly results from a dipole-induced greater barrier offset. However, the primary cause for defect generation at high field stress is attributed to the La atoms in the interfacial SiO2 layer. By optimizing the technique to incorporate nitrogen into the bottom interface, this high field reliability issue can be minimized while maintaining good device characteristics.

Tunnel Oxide Dipole Engineering in TANOS Flash Memory for Fast Programming with Good Retention and Endurance

Band engineering in TANOS (TaN-Al₂O₃-Si₃N₄-SiO₂-Silicon) Flash memory utilizing an interfacial dipole is demonstrated for the first time. A dipole layer at the tunnel oxide/charge storage layer interface leads to increase in programming speed while maintaining good retention and endurance. Using a dipole layer results in a 40% increase in Va, shift at program voltage V_g-V_fb, = 11 V. The performance improvement by dipole incorporation into the TANOS stack is discussed.

Device and reliability improvement of HfSiON+LaOx/metal gate stacks for 22nm node application

For the first time, we illustrate the importance of process sequence for LaOx capped HfSiON/metal gate on performance, variability, scaling, interface quality and reliability. La diffusion to the high-k/low-k interface controls V_t, as well as strongly affects mobility, N_it and BTI. La diffusion is limited to the Si surface by employing SiON interface layer (IL) mitigating the issues of La-induced mobility degradation and PBTI. Improved V_t tunability, reliability and performance are achieved with optimized process sequence, high-k thickness control, LaOx deposition and SiON (not SiO₂) IL. T_inv=1.15 nm and V_t,lin=0.31 V was obtained while achieving the following attributes: mobility~70%, N_it <5times10¹⁰ cm^-2, DeltaV_t<30 m V within wafer, BTI DeltaV_t <40 m V at 125degC. By optimizing these gate stack factors, we have developed and demonstrated structures for 22 nm node LOP application.

Effective surface passivation methodologies for high performance germanium metal oxide semiconductor field effect transistors

We demonstrate methodologies to improve the interface characteristics between a germanium (Ge) substrate and high-k gate dielectrics. GeON and SiOx were investigated as passivating layers on a Ge surface. Smaller hysteresis and interface state density (Dit) were obtained using SiOx interface layer and p-type metal oxide semiconductor field effect transistors (MOSFETs) fabricated with a gate stack of Ge/SiOx/HfSiO/WN showed about two times higher effective mobility compared to universal Si/SiO2 MOSFET. Because the formation of GeOx at the interface resulted in higher hysteresis and equivalent oxide thickness, the effective suppression of growth of unstable GeOx by SiOx interface layer contributed to the good device characteristics of the fabricated devices.

Aggressively Scaled High-k Gate Dielectric with Excellent Performance and High Temperature Stability for 32nm and Beyond

We demonstrate an amorphous higher-k (k>20) HfTiSiON gate dielectric for sub 32 nm node capable of low equivalent oxide thickness (EOT=0.84 nm). For the first time, we have addressed the thermodynamic instability of TiO2 containing gate dielectrics achieving an acceptably thin SiOx interface (0.7 nm) after 1070degC. 3-10times leakage current reduction is achieved with HfTiSiON vs. HfSiON due to a higher-k TiO2 cap (k=40) on HfSiON. For the first time, an 8% Ion-Ioff improvement of HfTiSiON vs. HfSiON is demonstrated. HfTiSiON shows Ion=1300 muA/mum at Ioff=100 nA/mum for Vdd=1.2 V without stress engineering. HfTiSiON shows bias temperature instability (PBTI) and time dependent dielectric breakdown (TDDB) similar to HfSiON. This work is significant because it demonstrates higher-k scaling benefit and extension of high-k beyond Hf-oxides for sub-32 nm technologies.

Gate First Band Edge High-k/Metal Stacks with EOT=0.74nm for 22nm Node nFETs

We demonstrate for the first time a gate first high-k/metal gate (MG) nFET with EOT = 0.74 nm (T_inv = 1.15 nm), low V_t = 0.30 V, high performance [I_on/I_Off = 1310(muA/um) at 100(nA/um)], low leakage (> 200x reduction vs. SiO₂/PolySi) and good PBTI. Low-k interface layer scaling and high-k La-doping enable this desirable EOT and V_t. SiON/HfLaSiON can give similar interface quality as SiO₂/HfSiON. Device performance was further improved 5% by strain engineering.