P.T. McDonald

Charge collection in silicon for ions of different energy but same linear energy transfer (LET)

Charge collection measurements in thin silicon structures have indicated that more charge is collected for higher energy ions than for the lower energy ions for incident ions with the same LET. The observed differences are larger than can be explained by uncertainties in energy-loss calculations. A possible explanation is in differences in initial track structure. The higher energy track is more diffuse and might yield more charge to be collected because there is less initial electron-hole pair recombination. >

Low temperature proton induced upsets in NMOS resistive load static RAM

Proton-induced upset measurements were performed on some NMOS resistive-load static RAMs for temperatures down to -125 degrees C. Results show that the upset cross section strongly depends on temperature as well as the incident beam flux. SPICE modeling for the critical charge versus temperature is not sufficient to explain the data. An explanation is provided that describes multiple subcritical linear-energy-transfer particle strikes within RAM cell integration times that cause upsets. >

The effects of radiation on MEMS accelerometers

Exposing just the mechanical part (sensor) of MEMS accelerometers to protons and heavy ions caused large changes in outputs representing the measured acceleration for the ADXL50 and very small changes for the ADXL04. The large voltage shift measured for the ADXL50 is attributed to charge generated by the ions and trapped in dielectric layers below the moveable mass. The trapped charge alters the electric field distribution which, in turn, changes the output voltage. The construction of the ADXL04 differs from that of the ADXL50 in that the dielectric layers are covered with a conducting polycrystalline silicon layer that effectively screens out the trapped charge, leaving the output voltage unchanged.

Pulsed laser-induced SEU in integrated circuits: a practical method for hardness assurance testing

A pulsed picosecond laser was used to measure the threshold for single event upset (SEU) and single event latchup (SEL) for a detailed study of a CMOS SRAM and a bipolar flip-flop. Comparing the ion and laser upset data for two such vastly different technologies gives a good measure of how versatile the technique is. The technique provided both consistent and repeatable results that agreed with published ion upset data for both types of circuits. However, measurements of the absolute threshold linear energy transfer (LET) using infrared laser light do not agree with those of the ions, being about 50% too high for the SRAMs, and about 20% too high for the bipolar flip-flops. The consistency of the results, together with the advantages of using a laser system, suggests that the pulsed laser can be used for SEU/SEL hardness assurance of integrated circuits. >

Charge Collection Efficiency Related to Damage in MOS Capaciors

Absolute charge collection efficiencies of undamaged and radiation damaged MOS capacitors have been measured as a function of applied collection bias and related to device damage. The measurements were performed on devices irradiated to various particle fluences, under different bias conditions, and with both lightly and heavily damaging particles. The measurements allow characterization and separation of damage effects due to flatband voltage shifts and atomic displacements in the substrate, and are sensitive indicators of both kinds of damage. Using this technique in conjunction with a microbeam, possibilities exist for investigating damage at a highly localized level, ion per ion, as the damage occurs. This technique is not limited to MOS devices.

Non-random single event upset trends

A macroscopic investigation of single-even-upset (SEU) trends for a class of CMOS/NMOS static RAMs exposed to heavy ions and protons has been performed. Analysis of the logical and spatial distribution of upsets as well as individual bit-upset polarity shows the need to consider the effects of peripheral circuitry interactions in understanding and modeling SEU phenomena, with important implications for spacecraft systems designs. Experimental studies and analysis of upset distributions along with SPICE modeling of the potential for word line upsets give a clear indication that upsets resulting from particle strikes on peripheral circuitry are occurring, and that the propagation of upsets along peripheral circuitry can have a serious impact on the numbers of logic word multiple upsets observed, depending on the layout of the device. >

A novel approach for measuring the radial distribution of charge in a heavy-ion track

We describe the design and uses of possible semiconductor test structures for measuring the initial radial distribution of charge and subsequent charge transport in a high energy, heavy-ion track. Numerical simulations show how the test structure can resolve different radial distributions of charge within an ion track. The test structure simulations also show the importance of accurately representing ion track structure in single event effects simulations. >

Analysis of single event effects at grazing angle

Investigation of single event effects at grazing angle by both charge collection and multiple bit upset measurements evidences modified collection mechanisms with charge transfer between adjacent reverse biased structures.

SEU rate prediction and measurement of GaAs SRAMs onboard the CRRES satellite

Upset rate predictions using heavy ion data are shown to overestimate the observed rates on CRRES (Combined Release and Radiation Effects Satellite) for the GaAs C-EJFET (complementary enhancement junctions FET) SRAM (static random-access memory) for both heavy ion and proton upset rates. The predicted heavy ion rates were an order of magnitude high, while the predicted proton upset rates were two orders of magnitude high. Predictions based on heavy ion data for the D-MESFET/resistor technology fell within an order of magnitude of the observed rate for both cosmic ray and proton upset rates. SPICE calculations underpredicted the upset rates for the C-EJFET SRAMs and overestimated the D-MESFET/resistor SRAM upset rates. The underestimate of comsic ray rates may be attributed to either a minimal assumption of collection depth or the possibility of enhanced charge collection. Incorrect use of the circuit-derived critical charge relative to the average measured critical charge would lead to the estimation of the heavy ion upset rate predictions for the D-MESFET/resistor SRAM. Observation of upset rates following onset of the solar flare event suggests that solar protons were responsible for high upset rates at the higher altitudes. >

Results from the CRRES MEP experiment

The effects of space radiation on microelectronics devices will be presented as measured by the Microelectronics Package Space Experiment on the Combined Release and Radiation Effects Satellite. >