Lloyd W. Massengill

Basic mechanisms and modeling of single-event upset in digital microelectronics

Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.

Charge Collection and Charge Sharing in a 130 nm CMOS Technology

Charge sharing between adjacent devices can lead to increased Single Event Upset (SEU) vulnerability. Key parameters affecting charge sharing are examined, and relative collected charge at the hit node and adjacent nodes are quantified. Results show that for a twin-well CMOS process, PMOS charge sharing can be effectively mitigated with the use of contacted guard-ring, whereas a combination of contacted guard-ring, nodal separation, and interdigitation is required to mitigate the NMOS charge sharing effect for the technology studied

Impact of scaling on soft-error rates in commercial microprocessors

The impact of technology scaling and logic design on the /spl alpha/-particle and neutron-induced soft-error rate (SER) of Alpha microprocessors (HP Alpha Development Group, Shrewsbury, MA) has been investigated. Our results indicate that the reduced charge-collection efficiency at the device level as well as circuit- and system-level mitigation techniques have successfully combatted the scaling trend of the critical charge. Process scaling and the introduction of flip-chip packaging have resulted in a nonnegligible contribution of /spl alpha/-particle-induced failure rates to the core-logic SER, whose overall importance has increased considerably since the implementation of error-correction codes.

Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design

A novel mechanism for upset is seen in a commercially available 0.25 /spl mu/m 10-T SEE hardened SRAM cell. Unlike traditional multiple node charge collection in which diffusions near a single event strike collect the deposited carriers, this new mechanism involves direct drift-diffusion collection at an NFET transistor in conjunction with parasitic bipolar conduction in nearby PFET transistors. The charge collection with the parasitic bipolar conduction compromise the SEE hardened design, thus causing upsets. The mechanism was identified using laser testing and three-dimensional TCAD simulations.

Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies

The distributions of SET pulse-widths produced by heavy ions in 130-nm and 90-nm CMOS technologies are measured experimentally using an autonomous pulse characterization technique. The event cross section is the highest for SET pulses between 400 ps to 700 ps in the 130-nm process, while it is dominated by SET pulses in the range of 500 ps to 900 ps in the 90-nm process. The increasing probability of longer SET pulses with scaling is a key factor determining combinational logic soft errors in advanced technologies. Mixed mode 3D-TCAD simulations demonstrate that the variation of pulse-width results from the variation in strike location.

The contribution of nuclear reactions to heavy ion single event upset cross-section measurements in a high-density SEU hardened SRAM

Heavy ion irradiation was simulated using a Geant4 based Monte-Carlo transport code. Electronic and nuclear physics were used to generate statistical profiles of charge deposition in the sensitive volume of an SEU hardened SRAM. Simulation results show that materials external to the sensitive volume can affect the experimentally measured cross-section curve.

Monte Carlo Simulation of Single Event Effects

In this paper, we describe a Monte Carlo approach for estimating the frequency and character of single event effects based on a combination of physical modeling of discrete radiation events, device simulations to estimate charge transport and collection, and circuit simulations to determine the effect of the collected charge. A mathematical analysis of the procedure reveals it to be closely related to the rectangular parallelepiped (RPP) rate prediction method. The results of these simulations show that event-to-event variation may have a significant impact when predicting the single-event rate in advanced spacecraft electronics. Specific criteria for supplementing established RPP-based single event analysis with Monte Carlo computations are discussed.

Single Event Transients in Digital CMOS—A Review

The creation of soft errors due to the propagation of single event transients (SETs) is a significant reliability challenge in modern CMOS logic. SET concerns continue to be exacerbated by Moores Law technology scaling. This paper presents a review of digital single event transient research, including: a brief historical overview of the emergence of SET phenomena, a review of the present understanding of SET mechanisms, a review of the state-of-the-art in SET testing and modelling, a discussion of mitigation techniques, and a discussion of the impact of technology scaling trends on future SET significance.

On-Chip Characterization of Single-Event Transient Pulsewidths

A new on-chip single-event transient (SET) test structure has been developed to autonomously characterize the widths of random SET pulses. Simulation results show measurement granularity of 900 ps for a 1.5 mum technology and also indicate that the measurement granularity rapidly scales down with technology. Laser tests were used to demonstrate circuit operation on test chips fabricated using a 1.5 mum process. The experimental results indicate pulsewidths varying from about 900 ps to over 3 ns as the laser energy was increased

Single-Event Transient Pulse Quenching in Advanced CMOS Logic Circuits

Heavy-ion broad-beam experiments on a 130 nm CMOS technology have shown anomalously-short single-event transient pulse widths. 3-D TCAD mixed-mode modeling in 90 nm and 130 nm bulk CMOS has identified a mechanism for simultaneous charge collection on proximal circuit nodes interacting in a way as to truncate, or ¿quench,¿ a propagated voltage transient, effectively limiting the observed SET pulse widths at high LET. This quenching mechanism is described and analyzed.