P. Waltz

Extensive analysis of resistance evolution due to electromigration induced degradation

Electromigration failure kinetic has been studied with resistance evolution versus time of interconnects during degradation. Tests were performed on dual damascene copper lines, issued from the 65 nm technology node, of various widths and lengths. All samples exhibit similar resistance evolution: an initial step, characterized by its height called Rstep, follows a linear kinetic characterized by its slope called Rslope. These two parameters were systematically extracted; Rstep is proportional to the critical volume of a void spanning the whole section of the line, and Rslope to the copper drift velocity. On one hand, the linewidth does not affect these two parameters. On the other hand, Rslope is highly dependent on the line length because of the Blech effect, while Rstep remains constant. Consequently, it was demonstrated that the classical linear function L/TTF=f(jL), where TTF is the time to failure, j is the current density, and L is the line length, used to study the Blech effect in interconnects cou...

Dielectrical properties of metal-insulator-metal aluminum nitride structures: Measurement and modeling

The electrical properties of polycrystalline aluminum nitride (AlN) films grown by reactive dc magnetron sputtering are investigated in the transient and the steady-state regimes through metal-insulator-metal (MIM) structures with molybdenum (Mo) as metal electrodes. Measurements of current-time, current-voltage, and current-temperature characteristics are performed on AlN MIM structures. The extracted dielectric constant is 9.9. The transient current is observed to follow the empirical Curie–Von Schweidler law and its dependence on the applied field and the operating temperature is modeled. The time approach result is compared with the frequency-approach result by measuring the permittivity dispersion for low frequencies. Also, all the leakage mechanisms in AlN are identified in the steady-state regime depending on the applied field range. For a low electric field, the conduction mechanism is the Ohmic regime and the AlN resistivity is estimated to be 2.1×1015 Ω cm at room temperature. For higher electri...

Review of fuse and antifuse solutions for advanced standard CMOS technologies

Specific applications require large amounts of high-performance, dense and low-cost non-volatile memories with CMOS standard process compatibility. There exists numerous structures for one-time-programming (OTP) bitcells, exploiting various physical phenomena as programming modes. Not all of these physical phenomena will behave in a satisfactory manner with the CMOS technology shrink. Moreover, it is not easy to evaluate the effect of geometry and technology on the trade-off between density and reliability of the OTP bitcells. This paper aims to review literature about OTP memories and show that metal fuse, polyfuse and antifuse are the best candidates so far. Other memories require either additional masks with regards to core process, additional technological steps or unaffordable programming conditions. Significant results will be listed in comparison tables. This paper also wishes to give a summary of the physical phenomena involved in bitcell architectures. Opinions are given about the suitability of OTP architectures for specific applications, the most suitable bitcell architectures have been layouted in 65 and 45nm for density comparison purpose. Particularly, promising structures are manufactured and characterized as they present fair trade offs for standard CMOS process. Discussion and conclusion are intended to give a comprehensive review about the parameters impacting the performances, the density and the cost of the OTP bitcell. Comparison tables are edited with the most pertinent parameters and available results.

Self heating under RF power in BAW SMR and its predictive 1D thermal model

This paper intends to provide a contribution for a better understanding of the self-heating effect in BAW SMR by developing a predictive 1D-model. Knowing the power dissipated inside the SMR, the presented model allows us estimating the temperature distribution inside the different layers of resonators used to build BAW filters. Model is compared with both experimental measurements and Finite Elements Analysis. Conclusions concerning the device reliability can eventually be drawn.

Electromigration induced void kinetics in Cu interconnects for advanced CMOS nodes

Time evolution of resistance during EM tests is extensively analyzed for various Cu interconnect structures and processes from the 40 nm node technology. Resistance evolution is used to model void nucleation and growth kinetics. We show that adding Al or other impurities in the line is effective to increase electromigration lifetime. This lifetime increase is due, as expected, to Cu drift velocity decrease but also to an increase of the time to void formation. TEM picture shows that Al precipitates are formed at grain boundaries and are most likely responsible for the occurrence of an incubation time Resistance saturation is observed for short lines thanks to Blech effect. A resistance model is developed to characterize short length effect in 40 nm node. The model is also used to explain EM lifetime improvement thanks to a pre-stress condition where compressive stress is added at cathode end of long line structures.

Grain boundary as relevant microstructure feature for electromigration in advanced technology studied by Electron BackScattered Diffraction

The work presented in this paper shows the links between electromigration (EM) in copper interconnects and microstructure of copper. Metal lines of 70 nm width corresponding to minimum width of 45–40 nm technology node are aged by electromigration (EM) test. Electron Backscattered Diffraction (EBSD) technique is then used to characterize microstructure and orientation of copper grains around void(s) resulting from EM. Advanced TEM and STEM characterization have also been used to assess reliability of EBSD technique (void localization, texture determination) applied to very small dimensions. Finally, the influence of cobalt (Co) as capping or sidewall liner and Aluminum-Copper alloy (CuAl) seed layer were investigated by EM tests and physical characterization. Our results confirm that critical microstructure parameter for electromigration phenomena in copper is grain boundary and in particular high angle misoriented grain boundaries.

Reliability issues related to Fast Charge Loss Mechanism in Embedded Non Volatile Memories

In this work, we report on a thorough study of charge loss in embedded non volatile memories. We focused on the fast initial threshold voltage (Vth) shift, which occurs during the first minutes of data retention bake. Experiments were performed to have a better understanding of this phenomenon. As a result, we can predict the Vth shift of a cell baked at 250degC and evaluate its impact on product reliability. This is the first time that this reliability aspect is characterized with such a level of accuracy. Based on these observations, a physical model is proposed to describe the fast initial threshold voltage shift

CU interconnect immortality criterion based on electromigration void growth saturation

The ever increasing scaling down of IC leads to ever more current density in interconnects. As a consequence, electromigration (EM) becomes a concern in interconnect reliability. In order to face this problem and allow more current density in design, one can take advantage of the Blech effect [1]. Many investigations have proposed extraction methods, behaviors or values for the threshold jLc product but some controversies subsist in particular on failures under jLc [2]. We studied the resistance saturation with time to characterize Blech effect of Cu/low-k dual damascene interconnects from the 65 nm node. We propose an immortality criterion proportional to the jL2 product based on the limitation of EM induced void volume at steady state. In our case, this criterion leads to more relaxed current rules for short lines compared to jLc criterion.

Microstructure and texture analysis of advanced copper using electron backscattered diffraction and scanning transmission electron microscopy

In this article, we focus on the characterization of copper interconnect by Electron Backscattered Diffraction (EBSD) in the final aim of reliability issue investigation. In a first time we demonstrate that we achieve to characterize copper lines of 70 nm width after some improvements in sample preparation. Then, after showing that EBSD is well adapted to characterize our structure even for very small dimensions (line width smaller than 100 nm), we propose to associate Transmission Electron Microscope in scanning mode (STEM) to complete information given by EBSD and localize defects due to electromigration. We begin by highlighting the very good correspondence between EBSD map and STEM images on line with small microstructure and finally we apply both techniques on a tested copper line after electromigration. In this case we show the relevance of using STEM to localize the defect due to electromigration which can not be seen on EBSD map.

Electron Backscattered Diffraction Analysis Of Narrow Copper Interconnects In Cross‐View To Investigate Scale Effect On Microstructure.

In this article, we propose to use Electron Backscattered Diffraction (EBSD) to characterize microstructure of copper interconnects of thin metal level in top view and cross view. These two views give very complementary information about microstructure of copper and thus about recrystallization of copper during annealing. Moreover, for minimum width, as interconnect is two times thicker than wide; It will be easier to analyze smaller interconnect of 45 nm node technology in cross‐section. We look for evolution of texture and microstructure of copper with line width in top view and in cross view. We highlight the presence of two recrystallization mechanisms and also the fact that transition from one to the other is progressive with competition of both mechanisms.