Philippe Candelier

A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM

A 1T cell for high-density eDRAM has been successfully developed on bulk silicon substrate for the first time. The device architecture is fully compatible with CMOS logic process integration, allowing very low chip cost for SoC applications. Experimental results show a retention time over 1s at 25/spl deg/C and 100ms at 85/spl deg/C, which is compatible with eDRAM requirements. Non-destructive readout is experimentally demonstrated at 85/spl deg/C. The integration of the memory cell in a matrix arrangement is evaluated. Gate and drain disturb are characterized, showing enough disturb margins for memory operations.

Further insight into the physics and modeling of floating-body capacitorless DRAMs

In this paper, we report on parasitic bipolar conduction occurring in floating-body effect based capacitor-less DRAMs. A way to include these effects into a previously developed model is presented. The enhanced model is then compared with electrical data realized on triple-well nMOSFET devices within the 26/spl deg/C-100/spl deg/C temperature range.

An 8 Mbit DRAM design using a 1 Tbulk cell

An 8 Mbit memory chip featuring a floating body one transistor cell on bulk substrate is characterized for the first time. A high-speed and high accuracy current sense-amplifier with a large common mode reference current is proposed. It achieves a reading time of 10 ns and a current read margin lower than 5 /spl mu/A. A bit fail rate of 0.017% was measured on a 1 Mbit module. Data retention shows that 1 Tbulk cell concept has the potential to be used as a future eDRAM memory cell.

Scaled IT-Bulk devices built with CMOS 90nm technology for low-cost eDRAM applications

A one transistor DRAM cell realized on bulk substrate (lT-Bulk) with CMOS 90nm platform is presented for the first time. The device fabrication is fully compatible with logic process integration and includes only few additional steps, thus making this IT cell very attractive for low-cost embedded memories. Very scaled devices were fabricated with a gate length down to 80nm and several gate oxide thicknesses: their performances in terms of memory effect amplitude, retention time and disturb margins are very promising for future high density eDRAM.

One time programmable drift antifuse cell reliability

An innovative non-volatile memory cell based on gate oxide breakdown is presented. The full compatibility with a standard CMOS process and the limited programming current per cell make the drift antifuse a low cost and dense non-volatile storage solution. Reliable storage is demonstrated and results from both device architecture and design optimization are given.

Simplified 0.35-μm flash EEPROM process using high-temperature oxide (HTO) deposited by LPCVD as interpoly dielectrics and peripheral transistors gate oxide

A simplified flash EEPROM process was developed using high-temperature LPCVD oxide both as flash cells interpoly dielectrics and as peripheral transistors gate oxide (decoding logic). An O/sub 2/ anneal at 850/spl deg/C lowers charge trapping and interface trap density induced by Fowler-Nordheim injection. However, electron trapping remains slightly higher than with dry thermal oxide. Similar memory charge loss and write-erase endurance are obtained as for ONO-insulated cells. HTO thus proves to have the required quality and reliability to be used in flash EEPROMs.

28nm advanced CMOS resistive RAM solution as embedded non-volatile memory

A back-end integrated Resistive Random Access Memory (ReRAM) (TiN/HfO2/Ti/TiN) in advanced 28nm CMOS process is evaluated. Significant operating margins and high performances identified at device level (read margin, low power set/reset, endurance and retention) are demonstrated to be significantly reduced on larger statistics, i.e. characterized within 1kbit arrays. The High Resistance State (HRS) dispersion, identified as a limiting factor, is modeled through the “tunneling barrier thickness” variation. The optimization through electrical condition tuning is discussed. A global overview of HfO2 material performances is assessed on statistical basis and projection for larger array integration is discussed.

A new extrapolation law for data-retention time-to-failure of nonvolatile memories

In this letter, we demonstrate that the commonly assumed Arrhenius law is inconsistent with extrapolation of data-retention time-to-failure of nonvolatile memories in highly accelerated life-tests. We argue that the retention time, namely log(t/sub H/), varies linearly with temperature T rather than with 1/T as commonly assumed, yielding an important reduction in the extrapolated time-to-failure. Extensive experimental results demonstrate the physical consistency of the new model. In particular, data-retention of EPROM devices and leakage current of interpoly dielectric and gate oxide have been investigated over a wide range of temperatures. Finally, it is shown that our model reconciles seemingly controversial activation energy data from the literature.

Review of fuse and antifuse solutions for advanced standard CMOS technologies

Specific applications require large amounts of high-performance, dense and low-cost non-volatile memories with CMOS standard process compatibility. There exists numerous structures for one-time-programming (OTP) bitcells, exploiting various physical phenomena as programming modes. Not all of these physical phenomena will behave in a satisfactory manner with the CMOS technology shrink. Moreover, it is not easy to evaluate the effect of geometry and technology on the trade-off between density and reliability of the OTP bitcells. This paper aims to review literature about OTP memories and show that metal fuse, polyfuse and antifuse are the best candidates so far. Other memories require either additional masks with regards to core process, additional technological steps or unaffordable programming conditions. Significant results will be listed in comparison tables. This paper also wishes to give a summary of the physical phenomena involved in bitcell architectures. Opinions are given about the suitability of OTP architectures for specific applications, the most suitable bitcell architectures have been layouted in 65 and 45nm for density comparison purpose. Particularly, promising structures are manufactured and characterized as they present fair trade offs for standard CMOS process. Discussion and conclusion are intended to give a comprehensive review about the parameters impacting the performances, the density and the cost of the OTP bitcell. Comparison tables are edited with the most pertinent parameters and available results.

Investigation of the impact of the oxide thickness and RESET conditions on disturb in HfO 2 -RRAM integrated in a 65nm CMOS technology

In this work, a comprehensive investigation of disturb in HfO2-Resistive Random Access Memories (RRAM) integrated in an advanced 65nm technology is presented. The effects of the oxide thickness and RESET conditions on disturb immunity of the High-Resistance-State (HRS) are explored. Constant Voltage Stress is applied on a large amount of samples at various temperatures. Data are collected and analyzed on a statistical basis. The SET dependence to the RESET conditions is investigated and correlated to the length of the induced depleted gap along the conductive filament. The conduction mechanism of the HRS is correlated to the failure/SET process of the RRAM device through a voltage acceleration model. It is shown that thicker dielectric oxide and stronger RESET conditions give rise to longer failure times.