Yaojian Lin

Next generation eWLB (embedded wafer level BGA) packaging

Demand for wafer level packaging (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. “Fan-in” (FI)-WLP typically has a limitation to be less than 6x6mm in order to pass board level reliability requirements such as drop test and temperature cycle due to the mismatch of Si material properties to the PCB. However, the “Fan-out” (FO)-WLP, has been developed and introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. The most prominent type of FO-WLP is the eWLB technology (embedded Wafer Level Ball Grid Array). Currently 1st generation eWLB technology is available in the industry. This paper will highlight some of the recent advancements in next generation eWLB technologies including multi-RDL, thin eWLB and extra large eWLB as well as double-side with vertical interconnection. These key technologies of next generation eWLB enable 3D eWLB applications such as SoW (SiP on Wafer) and 3D SiP. 3D eWLB can be implemented with through silicon via (TSV) applications as well as discrete component embedding. The process flow of next generation eWLB fabrication, assembly and packaging challenges will be discussed. This paper will also present some of the achievements in package reliability, mechanical characterization and performance.

Advanced low profile PoP solution with embedded wafer level PoP (eWLB-PoP) technology

Current portable electronic products are driving component packaging towards 3D packaging technologies for integrating multiple memory die and application processors (AP). Among the 3D technologies, Package-on-Package (PoP) is increasingly becoming mainstream due to its flexibility of combination and sourcing. Moreover, device designs require functional integration of ICs, especially in the 3rd dimension, hence driving new technology development towards making IC components “thin and thinner”. eWLB (embedded Wafer Level Ball Grid Array) has been introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. There is also great opportunity related to a 3D variation of eWLB which would allow for mounting of components or another package on the top surface with thinner profile and Package-on-Package (eWBL-PoP) technology. 3D PoP-eWLB is envisioned as an exciting technology which will open up the floodgates for system level integration utilizing very thin stacked eWLB packages as building blocks in mobile applications. This paper reports developments that are aimed to extend the low profile PoP application with eWLB + PoP technology. Test vehicle is designed and fabricated to demonstrate to be thin and 3D PoP solution for mobile and portable electronics. Assembly process details including laser ablation and interconnects process and mechanical characterizations are to be discussed with component and board level reliability results. Innovative package structures optimization that provide dual advantages of both form factor reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, package with multi layer redistribution (RDL) and 10um/10um line width/spacing is fabricated and implemented on eWLB platform. Successful reliability characterization results on low profile PoP package configurations are reported that demonstrate eWLB-PoP as an enabling technology for miniaturized, low profile and cost-effective 3D PoP.

Fanout flipchip eWLB (embedded Wafer Level Ball Grid Array) technology as 2.5D packaging solutions

The market for portable and mobile data access devices connected to a virtual cloud access point is exploding and driving both increased functional convergence as well as increased packaging complexity and sophistication. This is driving an unprecedented demand to increase the variety of wafer level, thin POP (Package on Package), and TSV (Through Silicon Via)/Interposer packaging solutions. It is expected to see more exciting interconnect technologies of wafer level packaging such as TSV, 2.5D Interposers, eWLB (embedded Wafer Level Ball Grid Array)/FO-WLP (Fan Out Wafer Level Package) to meet these needs. FO-WLP/eWLB has been introduced into production to allow for higher ball count WLP, by extending the package size beyond the area of the chip. eWLB technologies are leading the way to the next level of thin packaging capability. eWLB provides a robust packaging platform supporting very dense interconnection and routing of multiple-die in very reliable, low-profile/low-warpage 2.5D and 3D solutions. The use of these embedded FO-WLP packages in a side-by-side configuration to replace a stacked package configuration, and to utilize as the base for a 3D TSV configuration, is critical to enable a more cost effective mobile market capability. Combining the analog and memory device with digital device packaging capability can provide an optimum solution for achieving the best performance in thin multiple-die integration aimed at very high performance. This paper highlights the rapidly moving trend towards packaging technologies with extended-die/fanout flipchip technology. Package and substrate design study, mechanical and thermal characterization of flipchip eWLB solution over high-end flipchip would be presented.

Mechanical characterization of next generation eWLB (embedded wafer level BGA) packaging

Integrated Circuits fabricated on silicon are assembled in different forms of electronic packages and are used extensively in electronic products such as personal, portable, healthcare, entertainment, industrial, automotive, environmental and security systems. Current and future demand for these electronic systems in terms of performance, power consumption, reliable system at a reasonable price are met by developing advanced/appropriate silicon process technology, innovative packaging solutions with use of chip-package-system co-design, low cost materials, advanced assembly and reliable interconnect technologies. In this article packaging evolution for hand held application is discussed with special focus on next generation chip embedding technology called eWLB in detail. Currently 1st generation eWLB technology is available in the industry. This paper will highlight some of the recent advancements in component level and board level reliability of next generation eWLB technologies including multi-RDL, thin eWLB, extra large eWLB with multi-chip. Standard JEDEC tests were carried out to investigate component level reliability and both failure analysis was performed to investigate potential structural defects. Daisychain eWLBs were assembled with different package size and different configuration as like thin or multi-RDL or multi-die. Test vehicles were also tested for drop and TCoB (Temperature on Board) reliability in industry standard test conditions. Next generation test vehicles passed both drop and TCoB tests. There was more than 50% improvement of characteristic lifetime with thinned eWLB in TCoB test because of its enhanced flexibility of package. This paper also presents study of package warpage behavior with temperature profile which is important for understanding of mechanical behavior of next generation 3D eWLBs.

Three-stage bandpass filters implemented in silicon IPD technology using magnetic coupling between resonators

Thin-film technologies most commonly use capacitors or inductors to couple resonator stages for the implementation of band-pass filters. The use of mutual inductance (referred to as magnetically coupled, to distinguish it from conventional inductive coupling) has some inherent advantages, especially for ESD robustness and DC isolation. Furthermore, this method is naturally suited for the implementation of balanced filters. This paper describes the design and characterization of some example bandpass filters for wireless LAN applications in silicon IPD technology using capacitively-loaded ring resonators coupled by mutual inductance.

A Hybrid Coupled-Resonator Bandpass Filter Topology Implemented on Lossy Semiconductor Substrates

The Q of filter resonators formed on lossy substrates depends on their mode of excitation. Modifying the circuit design such that the voltage signals on resonator coils is predominantly differential can result in substantially higher Q. Band-pass filter resonator topologies that exploit this difference are discussed, and experimental results are presented for 802.11 b band-pass filters implemented in a thin-film technology on silicon substrates.

A finite element analysis of board level temperature cycling reliability of embedded wafer level BGA (eWLB) package

Three dimensional finite element analysis (FEA) is performed to assess the board level temperature cycling reliability for lead-free solder Sn96.5Ag3Cu0.5 (SAC305) used in eWLB packages. With Anand viscoplastic constitutive model used for the solder material, the chosen damage parameters, i.e. accumulated creep strain or accumulated creep strain energy density, can be derived from the finite element analysis (FEA) models and then can be correlated with the solder fatigue life obtained from the temperature cycling tests. In this study, a surface-based tie constraint technique is employed in the FEA models to facilitate mesh transition requirements at various interfaces of incompatible meshes. It is particularly the case arising from the die edges overlie the circular solder pads in the models. To deal with such situations, the FEA model for the entire package-to-board assembly can be strategically split into two parts and then connected to each other with tie constraints for the ease of meshing effort. It is found that this technique can help in managing a more uniform mesh distribution over the regions of interest, such as solder joints and dielectric layers with refine meshes, and yet allow a relatively coarse mesh to be assigned elsewhere for model size reduction. Thus, the computational efficiency for these tie-constraint models can be improved significantly as compared with their corresponding single part models with fine meshes and yet the model accuracy for the critical solder joint fatigue life estimation can be preserved. A model validation and numerical case study will be provided to illustrate the application of this modeling technique.

Encapsulated wafer level package technology (eWLCS)

This paper introduces a new encapsulated WLCSP product (eWLCS). The new product has a thin protective coating applied to all exposed silicon surfaces on the die. The applied coating protects the silicon and fragile dielectrics and prevents handling damage during dicing and assembly operations, effectively providing a durable packaged part in the form factor of a WLCSP. The manufacturing process leverages existing high volume manufacturing methods with exceptionally high process yields. In this process the silicon wafer is diced prior to the wafer level packaging process. The dice are then reconstituted into a new wafer form with adequate distance between the die to allow for a thin layer of protective coating to remain after final singulation. Standard methods are used to apply dielectrics, thin film metals, and solder bumps. The resulting structure is identical to a conventional WLCSP product with the addition of the protective sidewall coating. This paper discusses the key attributes of the new package as well as the manufacturing process used to create it. Reliability data will be presented and compared to conventional WLCSP products and improvements in package durability will be discussed and compared to conventional WLCSP.

Cost effective 300mm large scale eWLB (embedded Wafer Level BGA) technology

This paper will highlight some of the recent advancements in 300mm eWLB wafer development. Compared to 200mm case, 300mm eWLB wafer has more warpage and process issues due to its area increase. Thermo-mechanical simulation shows 100∼150% more warpage with 300mm eWLB wafer compared to 200mm. So various design parameters were studied to optimized warpage, such as dielectric materials and thickness, molding compound thickness etc. This paper also presents study of process optimization for 300mm eWLB and on overall warpage behavior in different process steps. Finally 300mm eWLB test vehicles are fabricated and tested in JEDEC standard test conditions. It also describes mechanical characterization, reliability data including component/board level, challenges encountered and overcome, and future steps.

WLCSP+ and eWLCSP in FlexLine: Innovative Wafer Level Package manufacturing

The demand for Wafer Level Chip Scale Packages (WLCSP) has experienced tremendous growth due to the surge in demand for advanced mobile products. The increased demand is seen for both 200mm wafers and 300mm wafers, however a significant segment of the market continues to be driven by 200mm designs. The infrastructure capacity supporting 200mm WLCSP has been stressed as a result of the mature status of 200mm technology and the rate of conversion of alternative package formats to WLCSP. This creates a dilemma for WLP service providers because adding 200mm capacity continues to require a significant amount of capital. Since 200mm volumes will most likely decline within the next 5 years, it is difficult to justify the purchase of capital when the depreciation term is longer than the anticipated life cycle of the product.