Seung Wook Yoon

High RF performance TSV silicon carrier for high frequency application

Three dimensional system-in-package (3D SiP) based on silicon carriers or interposer is a fast emerging technology that offers system design flexibility and integration of heterogeneous technologies. One of the key technologies enabler for silicon carrier is through silicon via (TSV). The development of 3D SiP will require the devices with different functionality operating at high frequency to be densely packed on the silicon substrate. However, silicon substrate is usually of low resistivity, when a high frequency signal is transmitted vertically through the substrate via, significant signal attenuation can occur that leads to poor RF performance. In this paper, a coaxial TSV structure in silicon carrier is presented for high frequency applications. The coaxial TSV is able to suppress undesirable substrate loss as well as provide good impedance matching. Electrical modeling of coaxial TSV structure was carried out to obtain the required geometries for impedance matching. Three different types of test vehicles were fabricated; Cu-plug TSV in both low (~10 Omega-cm) and high resistivity (~4000 Omega-cm) silicon substrate, and coaxial TSV in low resistivity silicon substrate. The S-parameters of the via structure of the test vehicles were measured from 100 MHz to 10 GHz. The measured results show that the coaxial TSV structure is able to suppress silicon substrate loss and provide good RF performance compared to Cu-plug TSV structure.

Electromigration in flip chip solder joints having a thick Cu column bump and a shallow solder interconnect

In advanced electronic products, current crowding induced electromigration failure is one of the serious problems in fine pitch flip chip solder joints. To explore a strong resistance against current crowding induced electromigration failure, a very thick Cu column bump combined with a shallow solder interconnect at 100μm pitch for flip chip applications has been studied in this paper. Results revealed that these interconnects do not fail after 720h of current stressing at 100°C with a current density of 1×104A∕cm2 based on the area of interface between Cu column bump and solder. The reduction of current crowding in the solder region by using thick Cu column bumps increased the reliability against electromigration induced failure. The current distribution in a flip chip joint of a Cu column bump combined with a shallow solder has been confirmed by simulation. However, Kirkendall void formation was found to be much serious and enhanced by electromigration at the Cu∕Cu3Sn interface due to the large Cu∕Sn ra...

Three-dimensional system-in-package using stacked silicon platform technology

In this paper, a novel method of fabricating three-dimensional (3-D) system-in-package (SiP) using a silicon carrier that can integrate known good dice with an integrated cooling solution is presented. The backbone of this stacked module is the fabrication of a silicon carrier with through-hole conductive interconnects. The design, process, and assembly to fabricate silicon through-hole interconnect using a wet silicon etching method is discussed in this paper. The process optimization to fabricate silicon carriers with solder through-hole interconnect within the design tolerance has been achieved. The design and modeling methodology to optimize the package in terms of electrical aspects of the stacked module is carried out to achieve less interconnect parasitics. An integrated cooling solution for 3-D stacked modules using single-phase and two-phase cooling solutions is also demonstrated for high-power applications. Known good thin flip-chip devices with daisy chain are fabricated and attached to the silicon carrier by flip-chip processes making it a known good carrier after electrical testing. Individual known good carriers are vertically integrated to form 3-D SiP.

A thick photoresist process for advanced wafer level packaging applications using JSR THB-151N negative tone UV photoresist

The development of thick photoresist molds using JSR THB-151N negative tone UV photoresist for the electroplating of interconnects in advanced packaging technologies has been demonstrated. Two different thick photoresist molds 65 and 130 µm high with aspect ratios of up to 2.6 have been fabricated with good reproducibility using single and double coating processes. Optimized lithography parameters using a UV aligner to achieve straight and near-vertical side-wall profiles are also reported. Near-vertical side walls similar to that obtained using SU-8 photoresist have been obtained. JSR photoresist has been found to be easily striped with no residues in solvent stripper solutions, making it suitable for wafer bumping applications and the processing of MEMS devices. Through-mold electroplating of copper and solder is also demonstrated. The simultaneous fabrication of 1167 000 high density interconnects on 8 inch wafers, using lithography and electroplating technologies, is also reported.

Fabrication of Silicon Carriers With TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Packages

This paper presents micro fabrication process and wafer-level integration of a silicon carrier, which consists of two Si chips that are bonded together with evaporated AuSn-solder. There are micro fins and channels fabricated in the Si chip and form the embedded cooling layer after bonding. The embedded cooling layer is connected with an inlet and an outlet to form a fluidic path for heat transfer enhancement. Besides, in the silicon carrier, there are through silicon vias (TSVs) with metal film on sidewall for electrical interconnection. Two or more carriers can then be stacked together with a silicon interposer in between to make up of a stacked cooling module for high power heat dissipation. The advantage of this 3-D stacking method is that it provides a method of simultaneously realizing electrical interconnection and fluidic path and it can extract heat from the constraints of 3-D silicon module chips to surface without external liquid circulation.

A thermodynamic study of phase equilibria in the Sn-Bi-Pb solder system

Abstract As a basis for the design and development of low-temperature solder alloys, the thermodynamic calculation of phase equilibria has been carried out on the binary Bi-Pb and ternary Sn-Bi-Pb systems over the entire composition range. The Gibbs free energy of individual phases has been approximated using the sub-regular solution model and thermodynamic parameters for each phase have been evaluated using available experimental information on phase boundaries and other related thermodynamic properties. The calculated phase diagrams and thermodynamic quantities of the Bi-Pb binary system show good agreement with the experimental data, and the liquidus projection and vertical sections in the Sn-Bi-Pb ternary system are well reproduced using assessed thermodynamic parameters derived in this work.

Development of low temperature bonding using in-based solders

In-based solders were chosen for the low temperature bonding at lower than 180degC. Three kinds of bonding types on Au/Cu/Ti/SiO2/Si dies, which were Sn/In and Au/In for Type 1, Au/In and Au/Sn for Type 2, and InSn alloy and InSn alloy for Type 3, were studied expecting that the whole In- solder layer is converted to the mixed intermetallic compound (IMC) phases of In-Cu and In-Au IMCs after bonding below 180degC and annealing at 100~120degC. The IMC in the joints were characterized in terms of the micro structure observations and the compositional analysis with Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray Spectroscopy (EDX), the phase identification with X-ray Diffraction (XRD) and the re-melting temperature with Differential Scanning Calorimetry (DSC). The phase equilibriums of the joints were examined by thermodynamic calculations to understand the re-melting behavior. As a result, complete bonding consisted of only high melting temperature IMCs, Cu11ln9, Cu2In, eta-Cu6Sn5, and Auln2, was successfully made at 120degC followed by annealing at 100degC in Type 3, and at 160degC with annealing for lOhrs or at 180degC without annealing for Type 1, which was confirmed by DSC measurements and explained through thermodynamic calculations.

Calculation of surface tension and wetting properties of Sn-Based solder alloys

This study has been supported by the Minstry of Science and Technology (MOST) through the Center for Interface Science and Engineering of Materials (CISEM)

Reliability of a Silicon Stacked Module for 3-D SiP Microsystem

Solder joint reliability of 3-D silicon carrier module were investigated with temperature cycle and drop impact test. Mechanical simulation was carried out to investigate the solder joint stress using finite element method (FEM), whose 3-D model was generated and solder fatigue model was used. According to the simulation results, the stress involved between flip chip and Si substrate was negligible but stress is more concentrated between Si carriers to printed circuit board (PCB) solder joint area. Test vehicles were fabricated using silicon fabrication processes such as DRIE, Cu via plating, SiO deposition, metal deposition, lithography, and dry or wet etching. After flip chip die and silicon substrate fabrication, they were assembled by flip chip bonding equipment and 3-D silicon stacked modules with three silicon substrate and flip chip dies were fabricated. Daisy chains were formed between flip chip dies and silicon substrate and resistance measurement was carried out with temperature cycle test (C, 2 cycles/h). The tested flip chip test vehicles passed T/C 5000 cycles and showed robust solder joint reliability without any underfill material. Drop test was also carried out by JEDEC standard method. More details on test vehicle fabrication and reliability test results would be presented in the paper.

Reliability studies of a through via silicon stacked module for 3D microsystem packaging

In this study, two types of reliability tests are studied for silicon stacked module. One is for temperature cycle solder joint reliability. Another is for drop impact test. Test vehicles are fabricated using silicon fabrication processes such as SiO2 deposition, metal deposition, lithography, through via formation, copper plating and dry or wet etching. After flipchip die and silicon substrate fabrication, they are assembled by flipchip bonder. Daisy chains are formed between flipchip dies and each silicon substrates and resistance measurement is carried out with temperature cycle test (-40/125degC, 2cycles/hr). In case of drop test, the JESD recommended condition B (e.g. 1500 G, 0.5 millisecond duration, and half-sine pulse) is adopted. And in-situ monitoring is carried out to observe the failure during the drop test. Reliability results of through via silicon stacked module indicated that it passed 1000 cycles T/C and survived drop impact test