Won Kyoung Choi

Development of low temperature bonding using in-based solders

In-based solders were chosen for the low temperature bonding at lower than 180degC. Three kinds of bonding types on Au/Cu/Ti/SiO2/Si dies, which were Sn/In and Au/In for Type 1, Au/In and Au/Sn for Type 2, and InSn alloy and InSn alloy for Type 3, were studied expecting that the whole In- solder layer is converted to the mixed intermetallic compound (IMC) phases of In-Cu and In-Au IMCs after bonding below 180degC and annealing at 100~120degC. The IMC in the joints were characterized in terms of the micro structure observations and the compositional analysis with Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray Spectroscopy (EDX), the phase identification with X-ray Diffraction (XRD) and the re-melting temperature with Differential Scanning Calorimetry (DSC). The phase equilibriums of the joints were examined by thermodynamic calculations to understand the re-melting behavior. As a result, complete bonding consisted of only high melting temperature IMCs, Cu11ln9, Cu2In, eta-Cu6Sn5, and Auln2, was successfully made at 120degC followed by annealing at 100degC in Type 3, and at 160degC with annealing for lOhrs or at 180degC without annealing for Type 1, which was confirmed by DSC measurements and explained through thermodynamic calculations.

The role of Ni buffer layer on high yield low temperature hermetic wafer bonding using In/Sn/Cu metallization

Low temperature hermetic wafer bonding using In/Sn interlayer and Au/Ni/Cu metallization as the high-melting-point (HMP) components was reported, wherein the thin Ni layer was introduced as a buffer layer to prevent solder consumption after their deposition. 8 in. wafer to wafer bonding was achieved at 180u2009°C for 20 min under 5.5 Mpa. Voids free seal joints composed of high temperature intermetallic compounds were obtained with good hermeticity. Present results show that the buffer layer is the key to ensure high yield hermetic wafer bonding when the low-melting-point solder was deposited directly on the HMP component.

Development of novel intermetallic joints using thin film indium based solder by low temperature bonding technology for 3D IC stacking

Low temperature bonding technology was developed using In-alloy on Au at a low temperature below 200 °C forming robust intermetallics (IMC) joints with high remelting temperature (≫300°C), so that after bonding, the IMC joints can withstand the subsequent processes without any degradation. Process parameters on the solder joint were optimized extensively in bonding and annealing process (temperature, time, and pressure). The joint fabricated at an optimal condition, which is 180°C for 45sec followed by annealing at 120°C for 12hrs, was evaluated in terms of microstructure and compositional observations by means of scanning electron microscope (SEM) and transmittance electron microscope (TEM). As a result, it was confirmed that the joint was completely occupied with the Au-In based IMC phases. And the re-melting temperature was measured as above 400°C by using Differential Scanning Calorimetery (DSC) and Thermo-Mechanical Analysis (TMA). This IMC joint showed a high bonding shear strength (≫20MPa) and a low electrical resistance (≪100mΩ). Based on this study, the 3 stacked dice with 8×8 mm2 dies with ∼1700 I/Os of 80um solder bumps were fabricated in a chip to chip stacking method. It showed uniform bonding all over the die in each layer and the high bonding strength of ∼40 MPa and passed the 3 times reflow test at 260 °C. The IMC joint reliability was examined. After going through the multiple reflows at 260°C, the bonded samples exhibited no delaminating and no changes in the bonding strength and the electrical resistance.

A novel, wafer-level stacking method for low-chip yield and non-uniform, chip-size wafers for MEMS and 3D SIP applications

Stacking of wafers with low chip-yield and non uniform chips size is developed for MEMS and 3D packaging applications. Stacking of MEMS and ASIC wafers one over other is difficult due to difference in chip yield and chip size. A cap wafer which is used for sealing the MEMS wafer in the wafer level package (WLP) is used for stacking the known good dice from MEMS wafer. Cavities and through silicon vias (TSV) are formed on a support wafer which matches with the ASIC (electronics) wafer. Based on the mapping of the ASIC wafer, a known good die from MEMS wafer is picked and attached into the support wafer. MEMS devices are attached in to the support wafer either by face down or face up with respect to ASIC chip. Redistribution lay outs are made on the ASIC wafer to match the pads configuration of the MEMS and ASIC wafer. The completed support wafer with MEMS devices in the cavity is bonded with ASIC wafer in a wafer bonder for final assembly. Since through hole vias are formed on the support wafer there is no need to etch through silicon via on either MEMS or AISC wafer. A hermetically sealed MEMS chip with ASIC one over other is assembled to meet the final real estate reduction of the package size. A stacking approach for low yield and non uniform chip size wafers is demonstrated.

Wafer-Level Hermetic Bonding Using Sn/In and Cu/Ti/Au Metallization

Low-temperature hermetic wafer bonding using In/Sn interlayer and Cu/Ti/Au metallization was investigated for microelectromechanical systems packaging application. In this case, the thin Ti layer was used as a buffer layer to prevent the diffusion between solder interlayer and Cu after deposition and to save more solders for diffusion bonding process. Bonding was performed in a wafer bonder at 180 and 150degC for 20 min with a pressure of 5.5 MPa. It was found that bonding at 180degC voids free seal joints composed of high-temperature intermetallic compounds were obtained with good hermeticity. However, with bonding at 150degC, voids were generated along the seal joint, which caused poor hermeticity compared with that bonded at 180degC. After four types of reliability tests-pressure cooker test, high humidity storage, high-temperature storage, and temperature cycling test-dies bonded at 180degC showed good reliability properties evidenced by hermeticity test and shear tests. Results presented here prove that high-yield and low-temperature hermetic bonding using Sn/In/Cu metallization with thin Ti buffer layer can be achieved.

A hermetic chip to chip bonding at low temperature with Cu/In/Sn/Cu joint

A bonding joint between Cu metallization and evaporated Sn/In composite solder was produced at temperature lower than 200degC in air in this work. The isothermal solidification and subsequent interdiffusion of Cu and Sn/In took place along the bonding couples held at 180degC for 20 minutes. The interfacial reaction and the bonding quality is studied and evaluated. Scanning electron microscopy (SEM) exhibits the joint is uniform along the bonding interface and no crack or voids present, which has an interfacial tensile strength of 52 kg/cm2. The overall bonding is examined by C-mode scanning acoustic microscope (C-SAM). Fine leak rate test shows the leak rate is about 5.8x10-9 arm-cc/s which indicates a hermetic sealing. Intermetallic compounds (IMCs) such as Auln2, Cu6Sn5 and Cu11ln9 have been detected by means of X-ray diffraction analysis (XRD) and transmission electron microscopy (TEM) accompanied with energy dispersive X-ray (EDX). The chemical composition analysis also reveals that solder interlayers, Sn and In, have been completely converted into IMCs by reacting with Cu. All IMCs formed in the joints have re-melting temperature above 300degC according to Cu-In, Cu-Sn and Au-In phase diagrams. Therefore, the joint can sustain high service temperature due to the presence of IMCs. Such technique producing the joints with the good bond quality and high re-melting point has great potential in electronics and microelectronics packaging such as MEMS packaging and photonic packaging.

A novel die to wafer (D2W) collective bonding method for MEMS and electronics heterogeneous 3D integration

A new D2W collective bonding approach is demonstrated with functional MEMS devices with smaller than 3 × 3 mm2 and 8 inch ASIC wafers. The new package design was proposed in order to reduce the parasitic effect by attaching the released MEMS dice directly to the pads on an ASIC wafer. Two different types of MEMS devices having combs structure and a beam structure were used in order to confirm the minimal change in the MEMS functionality before and after D2W bonding. The ASIC wafer consisted of non functional circuit with pads and the daisy chain for measuring the electrical resistance and interconnection lead-out. With the new method by utilizing both the standard pick and place machine and the wafer bonder, ~ 800 numbers of functional MEMS dice were bonded to ASIC by low temperature D2W collective bonding at 200 degC for 2 minutes having an alignment tolerance less than 10% in 150 μm pitch with pad size of 75 μm. In this approach, the bonding time has been reduced by more than 50% in comparison with the conventional D2W bonding with flip chip bonder and performance of the package was improved by direct interconnection and the yield was improved by bonding with Known Good Dice.

Low-Stress Bond Pad Design for Low-Temperature Solder Interconnections on Through-Silicon Vias (TSVs)

Low temperature bonds are thin intermetallic bonds that are formed between devices when plated layers of different metals on each side of the component come into contact under relatively low temperature and high pressure. These joints comprised completely of intermetallic compounds, will fail in a sudden unexpected manner, compared to normal solder joints which fail in a ductile manner where cracks grow more slowly. This problem of weak interconnects is further exacerbated when these thin interconnections are formed on pads located above through-silicon vias (TSVs). When a change in temperature occurs, the mismatch in coefficient of thermal expansion (CTE) causes the copper inside the TSV to expand or contract much more than the surrounding silicon. This could result in unexpectedly high tensile stresses in the joints. This additional tensile stress on post-formation cooling to room temperature increases the likelihood of joint failure. This paper presents a novel pad design to overcome the situation of high stress in the joints. The proposed design does not involve any additional fabrication or material cost. Simulation results show that with the proposed pad design, the maximum tensile stress in the interconnect decreases by 50%. Reliability assessment has also done in order to compare the proposed pad design with the conventional design. It is found that the samples with the proposed design have a better drop impact reliability performance and higher shear strength than the samples with the usual pad design.

Design, simulation and process optimization of AuInSn low temperature TLP bonding for 3D IC Stacking

An IMC based low temperature solder <200 °C with AuInSn composition is developed for 3D IC stacking application. Thermodynamic and mechanical simulations are conducted to study the phase change during the melting temperature and the stress due to the thin solder material. A three layer stack bonding with the developed solder has been characterized after bonding and reliability test. It is found that no degradation in shear strength and compositional structure of the solder and is verified by the TEM cross sectional structure with EDX analysis. A 3D IC structure with TSV test vehicle is designed and demonstrated the low temperature solder application. C2W bonding approach is used for the 3D IC stack bonding method and is found suitable for devices with TSV structure. Final reliability test with daisy chain structure and TSV showed <10% resistance increase in majority of interconnections after 1000 cycles of thermal cycle test.

Thin die stacking by low temperature In/ Au IMC based bonding method

Low temperature bonding technology is developed using In-alloy on Au at a low temperature below 200˚C forming robust intermetallics (IMC) joints with high re-melting temperature (>300˚C), so that after bonding the IMC joints can withstand the subsequent processes without any degradation. Using similarly solder system and methodology, chips to wafer (C2W) bonding method has been developed, as such chips are temporary bonded onto wafer before the final bonding. The chips are bonded onto the wafer by two sequential bonding condition; temporary followed by a final bonding, which is 200/90˚C (chip/wafer) for 20sec and 180/180˚C for 5mins. The IMC joints are evaluated in terms of microstructure and compositional observations by means of scanning electron microscope (SEM) and transmittance electron microscope (TEM). As a result, it was confirmed that the joint was completely occupied with the Au-In based IMC phases. These IMC joint showed a tensile strength of 120~330N (23.5~38.8MPa). Based on this study, the 3 stacked dice with 8×8 mm2 dies with ~1700 I/Os of 80um solder bumps were fabricated in a chip to wafer stacking method. It showed uniform bonding all over the die in each layer with relatively good tensile strength achieved. Furthermore, it also underwent 3 times reflow test at 260˚C. The IMC joint was examined after going through the reflows test and the bonded samples exhibited neither de-lamination nor any changes in the microstructure.