Pang-Yen Tsai

High density 3D integration using CMOS foundry technologies for 28 nm node and beyond

Technology challenges and solutions in the development and fabrication of high-density three dimensional (3D) chip integration structures have been investigated. Critical 3D integrated circuit (IC) enabling technologies, such as through silicon via (TSV), wiring and redistribution layer (RDL), wafer thinning and handling, micro-bump (µ-bump) processes and joining, that form the building blocks for 3D IC technology were developed based on established Si foundry technologies. Test vehicles (TVs) have been designed to develop and optimize the processes, structures, as well as to evaluate the performance, yield and reliability of the 3D integration scheme.

Low power device technology with SiGe channel, HfSiON, and poly-Si gate

We report solutions to the formidable challenges posed by integrating a HfSiON dielectric with a poly-Si gate for low-power device technology. A 1.5 nm EOT HfSiON is demonstrated with mobility comparable to SiO/sub 2/ and 3 orders of magnitude leakage reduction. A novel boron delta-doped strained-SiGe channel points a way out of the high threshold voltage problem associated with Fermi-pinning at the high-k/poly-Si interface and ameliorates short-channel effects in PMOS devices. In addition, a 20% hole mobility enhancement and 15% I/sub on/-I/sub off/ characteristics improvement are achieved owing to the compressive SiGe channel. NMOS PBTI lifetime of 35 years, and PMOS NBTI and NMOS hot carrier lifetimes of more than 1000 years are demonstrated at 1.2 V.