Parsotam Trikam Patel

IBM RISC chip design methodology

An overview is given of the chip design methodology of the IBM Austin, Texas Advanced Workstation Division. The primary components of this methodology are a high-level language (DSL); a common database (CDB); synthesis, simulation, and floor planning tools; and custom-built circuit elements. The methodology and tools support a top-down design that begins with a high-level logic specification. The hierarchical nature of the methodology permeates all aspects of the design environment, beginning with logic entry, proceeding through physical implementation, and terminating with checking. New additions to the methodology include a high-level language, a synthesis tool, a hardware simulator, a third metal layer for better IO handling, a new min-cut placement program, and an RC estimator/calculator.<<ETX>>