Howard Leo Kalter

A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC

A high-speed 16-Mb DRAM chip with on-chip error-correcting code (ECC), which supports either 11/11 or 12/0 RAS/CAS addressing and operates on a 3.3- or 5-V power supply, is described. It can be packaged as a 2-Mb*8, 4-Mb*4, 8-Mb*2, or 16-Mb*1 DRAM, And is capable of operating in fast page mode, static column mode, or toggle mode. Speed and flexibility are achieved by a pipeline layout and on-chip SRAMs that buffer entire ECC words. The use of redundant word and bit lines in conjunction with the ECC produces a synergistic fault-tolerance effect. >

Processor-based built-in self-test for embedded DRAM

A built-in self-test engine and test methodology have been developed for testing a family of high-bandwidth, high-density DRAM macros. The DRAM macros range in size from 256/spl times/16/spl times/128 to 2 K/spl times/16/spl times/256 (Word/spl times/Bit/spl times/Data) and are targeted for embedded applications in application-specific integrated circuit designs. The processor-based test engine, with two separate instruction storage memories, combines with flexible address, data, and clock generators to provide DRAM high-performance ac testing using a minimum of dedicated test pins. Test results are compressed through on-macro, two-dimensional, redundancy allocation logic to provide direct programming information for the fuser via a serial scan port. The design is intended for reuse on future DRAM-generation subarrays and can be adapted to any number of address or data-pin configurations.

High-reliability fault-tolerant 16-MBit memory chip

A combination of redundant circuits and error-correcting-code circuits have been implemented on a 16-Mb memory chip. The combination of these circuits results in a synergistic fault-tolerance scheme that makes this chip immune to a high level of manufacturing and reliability defects. Experiments have been performed with highly defective chips to test the error-correction capability of this chip and to determine models for the tradeoff between manufacturing yields and reliability. Additional experiments have been done with accelerated protons to investigate the soft-error sensitivity of this chip. Results show no soft-error reliability failures, including those caused by cosmic-particle radiation. Negative binomial distributions were used to evaluate the experiments. The correlation between manufacturing-faults and stress-failures were modeled with a bivariate negative-binomial distribution. >

An experimental 80-ns 1-Mbit DRAM with fast page operation

An experimental general purpose 5-V 1-Mb dynamic RAM has been designed for increased performance, high density, and enhanced reliability. The array consists of a one-device overlapped I/O cell with a metal bitline architecture. The cell measures 4.1 /spl mu/m by 8.8 /spl mu/m, which yields a chip size of 5.5 mm by 10.5 mm with an array to chip area ratio of 65.5%. The chip was designed in a double-poly single-metal NMOS technology with selected 1-/spl mu/m levels and an average feature size of 1.5 /spl mu/m. Key design features include a fast page mode cycle with minimum column precharge delay and improved protection for short error rate using a boosted word-line after sense amplifier set scheme. The CAS access time is 40 ns and the cycle is 65 ns at 4.5 V and 85/spl deg/C. The RAS access time is 80 ns and the cycle is 160 ns at 4.5 V and 85/spl deg/C with a typical active power of 625 mW. The chip is usable as a X1, X2, or X4 with the use of block select inputs and the selected package option. The package options include a 500-mil/SUP 2/ pin grid array module with 23 pins, and a 22 pin or 26 pin 300-mil surface solder plastic package.

High-reliability fault-tolerant 16 Mbit memory chip

A combination of redundant circuits and error-correcting-code circuits have been implemented on a 16 Mb memory chip. The combination of these circuits results in a synergistic fault-tolerance scheme, making this chip immune to a high level of manufacturing and reliability defects. In addition to the error-correcting-code circuits, the chip also has redundant cells that can be used to replace defective cells. The combined use of the error-correcting code, and redundancy results in a synergetic fault-tolerance effect, making the chip impervious to thousands of manufacturing defects. This is an increase in fault tolerance of several orders of magnitude.<<ETX>>

A 2.5-V 16-Mb DRAM in 0.5-/spl mu/m CMOS technology

Low-voltage circuit techniques for high-density DRAMs, and the utilization of these techniques on a 16-Mb DRAM operating over the 2.5-V specification range, are presented. The P-type array is designed using full-V/sub cc/ bit line precharge for fast signal development and optimal sense latch sensitivity. Performance and power are further enhanced by using a digital secondary sense amplifier (DSSA). A worst-case module access of 55 ns is obtained from chips fabricated in 0.5-/spl mu/m CMOS technology.

A 50 ns 16 Mb DRAM with a 10 ns data rate

A 16-Mb DRAM chip fabricated in a 0.5- mu m CMOS process using silicided polysilicon, double metal, and trench storage is described. It incorporates an architecture that supports either 11/11 or 12/10 RAS/CAS (row-address strobe/column-address-strobe) addressing. It is segmented to utilize bit redundancy of 2 lines/137-b lines/half quadrant, and separate word-redundant array of 24 lines/quadrant, providing any-for-any-word-line replacement within a quadrant. It has single-error-correct/double-error-detect (SEC/DED) error checking and correcting (ECC) Hamming odd-weight code/quadrant and either 5-V or 3-V operation. The design provides a RAS access of 50 ns with 16-ns fast-page access, 18-ns static column or toggle of 10 ns at 2.9 V and 85 degrees C. DRAM features are summarized.<<ETX>>

Design for reliability, testability and manufacturability of memory chips

The number of transistors on integrated-circuit chips is growing exponentially. This makes it increasingly difficult to satisfy the continuing demand for ever higher reliability of chips. The tools available to the chip architects and circuit designers for solving this predicament are discussed. The solutions include correct circuit placement and chip segmentation; logic and timing interlocks; low internal chip noise; optimized performance; circuits designed for ease of testability and for detectability of all defects; reduced sensitivity to manufacturing defects with relaxed layouts; wear-out mechanisms minimized by design; and low power consumption for reduced operating junction temperatures. These solutions and the design practices described have been implemented on 16-Mb and 18-Mb DRAM (dynamic random access memory) chips, each having more than 20 million transistors.<<ETX>>

Multipurpose DRAM architecture for optimal power, performance, and product flexibility

An 18Mb DRAM has been designed in a 3.34, 0.5-pm CMOS process. The array consists of four independent, self-contained 4.5Mb quadrants. The chip output configuration defaults to 1 Mb x 18 for optimization of wafer screen tests, while 3 .34 or 5.04 operation is selected by choosing one of two M2 configurations. Selection of 2Mb x 9 or 1 Mb x 18 operation with the various address options, in extended data-out or fast-page mode, is accomplished by selective wire-bonding during module build. Laser fuses enable yield enhancement by substituting eight 512Kb array I/O slices for nine in each quadrant of the 18Mb array. This substitution is independent in each quadrant and results in 1 Mb x 16 operation with 2Mb x 8, 4Mb x 4, and 4Mb x 4 with any 4Mb independently selectable (4Mb x 4 w/4 CE). Input and control circuitry are designed such that performance margins are constant across output and functional configurations. The architecture also provides for “cut-downs” to 16Mb, 4.5Mb, and 4Mb chips with I/O and function as above.